[Intel-gfx] [PATCH 1/3] drm/i915: Keep the ctx workarounds tightly packed

[Ville Syrjälä]

On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote:
> 
> 
> On 6/15/2018 1:59 AM, Chris Wilson wrote:
> > For each platform, we have a few registers that rewritten with multiple
> > values -- they are not part of a sequence, just different parts of a
> > masked register set at different times (e.g. platform and gen
> > workarounds). Consolidate these into a single register write to keep the
> > table compact.
> >
> > While adjusting the construction of the wa table, make it non fatal so
> > that the driver still loads but keeping the warning and extra details
> > for inspection.
> 
> A while ago I sent a patch 
> (https://patchwork.freedesktop.org/patch/205035/) that uses simple MMIO 
> writes to apply ctx workarounds. This is possible since we now have 
> proper golden contexts, and avoids the need for these patches.
> It also has the advantage that an improperly classified WA doesn't get 
> lost (we still need the classification if we want to properly validate 
> the WAs, but that's a different story).
> Are we sure we prefer to do this instead?

Wouldn't that require PSMI+FSM dance to make sure execlist has
an active context when you write the regs? Can't see anything like that
in the code currently, nor is there anything in the referenced patch.

-- 
Ville Syrjälä
Intel