[Intel-gfx] [PATCH 23/24] drm/i915/icl: program MG_DP_MODE

[Maarten Lankhorst]

Op 19-06-18 om 14:59 schreef Maarten Lankhorst:
> Op 22-05-18 om 02:25 schreef Paulo Zanoni:
>> Programming this register is part of the Enable Sequence for
>> DisplayPort on ICL. Do as the spec says.
>>
>> Cc: Animesh Manna <animesh.manna at intel.com>
>> Cc: Manasi Navare <manasi.d.navare at intel.com>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h  | 15 +++++++++
>>  drivers/gpu/drm/i915/intel_ddi.c |  2 ++
>>  drivers/gpu/drm/i915/intel_dp.c  | 66 ++++++++++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>>  4 files changed, 84 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 2a501e7590bf..2ccae6c3e905 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1943,6 +1943,21 @@ enum i915_power_well_id {
>>  #define CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
>>  #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK			(0x3F << 16)
>>  
>> +#define _MG_DP_MODE_LN0_ACU_PORT1			0x1683A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT1			0x1687A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT2			0x1693A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT2			0x1697A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT3			0x16A3A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT3			0x16A7A0
>> +#define _MG_DP_MODE_LN0_ACU_PORT4			0x16B3A0
>> +#define _MG_DP_MODE_LN1_ACU_PORT4			0x16B7A0
>> +#define MG_DP_MODE(port, ln)	\
>> +	_ICL_MG_PHY_PORT_LN(port, ln, _MG_DP_MODE_LN0_ACU_PORT1, \
>> +				      _MG_DP_MODE_LN0_ACU_PORT2, \
>> +				      _MG_DP_MODE_LN1_ACU_PORT1)
>> +#define   MG_DP_MODE_CFG_DP_X2_MODE			(1 << 7)
>> +#define   MG_DP_MODE_CFG_DP_X1_MODE			(1 << 6)
>> +
>>  /* The spec defines this only for BXT PHY0, but lets assume that this
>>   * would exist for PHY1 too if it had a second channel.
>>   */
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index 1d5bfec57c33..c3c29565b863 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2667,6 +2667,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>>  
>>  	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>>  
>> +	icl_program_mg_dp_mode(intel_dp);
>> +
>>  	if (IS_ICELAKE(dev_priv))
>>  		icl_ddi_vswing_sequence(encoder, level, encoder->type);
>>  	else if (IS_CANNONLAKE(dev_priv))
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index a883a3264e56..1228d6185f76 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -229,6 +229,72 @@ intel_dp_link_required(int pixel_clock, int bpp)
>>  	return DIV_ROUND_UP(pixel_clock * bpp, 8);
>>  }
>>  
>> +void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
>> +{
>> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> +	struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>> +	enum port port = intel_dig_port->base.port;
>> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>> +	u32 ln0, ln1, lane_info;
>> +
>> +	if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
>> +		return;
>> +
>> +	ln0 = I915_READ(MG_DP_MODE(port, 0));
>> +	ln1 = I915_READ(MG_DP_MODE(port, 1));
>> +
>> +	switch (intel_dig_port->tc_type) {
>> +	case TC_PORT_TYPEC:
>> +		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>> +		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
>> +
>> +		lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>> +			     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>> +			    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>> +
>> +		switch (lane_info) {
>> +		case 0x1:
>> +		case 0x4:
>> +			break;
> Shouldn't this still be x1 mode?
Ah nm, found the mapping.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>