[Intel-gfx] [PATCH V2] drm/i915: Use I915_MAP_WC for execlists context buffer on the platforms without LLC

[Zhao, Yakui]

>-----Original Message-----
>From: Chris Wilson [mailto:chris at chris-wilson.co.uk]
>Sent: Friday, June 22, 2018 2:26 PM
>To: Zhao, Yakui <yakui.zhao at intel.com>; intel-gfx at lists.freedesktop.org
>Cc: Zhao, Yakui <yakui.zhao at intel.com>
>Subject: Re: [PATCH V2] drm/i915: Use I915_MAP_WC for execlists context
>buffer on the platforms without LLC
>
>Quoting Zhao Yakui (2018-06-22 07:09:10)
>> Under execlists mode the context buffer is allocated in global Gtt region.
>> The I915_MAP_WB type is used to map the buffer so that the driver can
>> initialize the context buffer.(Ring reg, Context Ctrl reg and so on).
>> And then __context_pin is called to flush back corresponding contents.
>> In fact as it also tries to update context buffer (Ring Tail offset)
>> before writing the ELSP port, it has no explicit cache flsuh.Maybe it
>> is handled by HW. But this is quite confusing as BXT has no LLC. So
>> the WC is used to map the context buffer on the platform without LLC
>> and the update of context buffer is writen into phys page directly. It
>> will be safer.
>>
>> V1->V2: Remove the dirty flag of execlists state buffer and one minor
>> typo in commit log
>
>The object's pages are still dirty, so why? It's not about CPU cache dirt, here it
>is about whether the pages differ from any potential swapcache.
>

Based on the test it seems that this patch still has some problems. More works are needed in order to change the MAP type.
Maybe this buffer should be handled like intel_ring biffer.
I will check it later.

>I was anticipating there would be some type conflict with
>engine->pinned_default_state, but that just happens to work out
>correctly... so long as there is always a retirement during load and we park
>before any reset. Hmm.
>-Chris