[Intel-gfx] [i-g-t] tests/kms_plane_multiple: DDB corner testcase
Karthik B S
karthik.b.s at intel.com
Thu Jun 28 13:03:05 UTC 2018
This is to exercise DDB algorithm corner case where
DDB allocation was not happening properly for varying size plane.
Current DDB algorithm uses datarate based DDB division among
planes, but planes with same width require same DDB allocation
irrespective of their height.
To address this a Multiplane flip is added, with all planes other
than the topmost plane having full size, and the top most plane
size and position is varied.
Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
Signed-off-by: Karthik B S <karthik.b.s at intel.com>
---
tests/kms_plane_multiple.c | 130 ++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 116 insertions(+), 14 deletions(-)
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index e61bc84..e9ebaeb 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -35,6 +35,8 @@ IGT_TEST_DESCRIPTION("Test atomic mode setting with multiple planes ");
#define SIZE_PLANE 256
#define SIZE_CURSOR 128
#define LOOP_FOREVER -1
+#define TEST_DDB_ALGO 1
+#define SIZE_PANE 10
typedef struct {
float red;
@@ -48,6 +50,7 @@ typedef struct {
igt_crc_t ref_crc;
igt_pipe_crc_t *pipe_crc;
igt_plane_t **plane;
+ unsigned int flag;
struct igt_fb *fb;
} data_t;
@@ -62,6 +65,14 @@ struct {
.seed = 1,
};
+enum position {
+ POS_TOP,
+ POS_LEFT,
+ POS_BOTTOM,
+ POS_RIGHT,
+ POS_MAX,
+};
+
/*
* Common code across all tests, acting on data_t
*/
@@ -242,6 +253,80 @@ prepare_planes(data_t *data, enum pipe pipe_id, color_t *color,
}
static void
+prepare_planes2(data_t *data, enum pipe pipe_id, color_t *color,
+ uint64_t tiling, int max_planes, igt_output_t *output,
+ enum position position)
+{
+ drmModeModeInfo *mode;
+ int x;
+ int y;
+ int i;
+ int hsize, vsize;
+
+ mode = igt_output_get_mode(output);
+
+ for (i = 0; i < max_planes; i++) {
+ igt_plane_t *plane = igt_output_get_plane(output, i);
+ uint32_t format = DRM_FORMAT_XRGB8888;
+
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ format = DRM_FORMAT_ARGB8888;
+ tiling = LOCAL_DRM_FORMAT_MOD_NONE;
+ x = 0;
+ y = 0;
+ hsize = SIZE_CURSOR;
+ vsize = SIZE_CURSOR;
+ } else if ((plane->index == max_planes - 2) &&
+ (plane->type != DRM_PLANE_TYPE_PRIMARY)) {
+ /* Top most plane and not the primary plane */
+ switch (position) {
+ case POS_TOP:
+ x = 0;
+ y = 0;
+ hsize = mode->hdisplay;
+ vsize = SIZE_PANE;
+ break;
+ case POS_RIGHT:
+ x = mode->hdisplay - SIZE_PANE;
+ y = 0;
+ hsize = SIZE_PANE;
+ vsize = mode->vdisplay;
+ break;
+ case POS_BOTTOM:
+ x = 0;
+ y = mode->vdisplay - SIZE_PANE;
+ hsize = mode->hdisplay;
+ vsize = SIZE_PANE;
+ break;
+ case POS_LEFT:
+ x = 0;
+ y = 0;
+ hsize = SIZE_PANE;
+ vsize = mode->vdisplay;
+ break;
+ default:
+ igt_info("Invalid Position\n");
+ }
+
+ } else {
+ x = 0;
+ y = 0;
+ hsize = mode->hdisplay;
+ vsize = mode->vdisplay;
+ }
+
+ data->plane[i] = plane;
+ igt_create_color_fb(data->drm_fd,
+ hsize, vsize,
+ format, tiling,
+ color->red, color->green, color->blue,
+ &data->fb[i]);
+ igt_plane_set_position(data->plane[i], x, y);
+ igt_plane_set_fb(data->plane[i], &data->fb[i]);
+ }
+}
+
+static void
test_plane_position_with_output(data_t *data, enum pipe pipe,
igt_output_t *output, int n_planes,
uint64_t tiling)
@@ -267,21 +352,29 @@ test_plane_position_with_output(data_t *data, enum pipe pipe,
info, opt.seed);
test_init(data, pipe, n_planes);
-
test_grab_crc(data, output, pipe, &blue, tiling);
- i = 0;
- while (i < iterations || loop_forever) {
- prepare_planes(data, pipe, &blue, tiling, n_planes, output);
+ if (data->flag == TEST_DDB_ALGO) {
+ for (i = POS_TOP; i < POS_MAX; i++) {
+ prepare_planes2(data, pipe, &blue, tiling,
+ n_planes, output, i);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
+ }
+ i = 0;
+ } else {
+ while (i < iterations || loop_forever) {
+ prepare_planes(data, pipe, &blue, tiling,
+ n_planes, output);
- igt_display_commit2(&data->display, COMMIT_ATOMIC);
+ igt_display_commit2(&data->display, COMMIT_ATOMIC);
- igt_pipe_crc_drain(data->pipe_crc);
- igt_pipe_crc_get_single(data->pipe_crc, &crc);
+ igt_pipe_crc_drain(data->pipe_crc);
+ igt_pipe_crc_get_single(data->pipe_crc, &crc);
- igt_assert_crc_equal(&data->ref_crc, &crc);
+ igt_assert_crc_equal(&data->ref_crc, &crc);
- i++;
+ i++;
+ }
}
test_fini(data, output, n_planes);
@@ -318,7 +411,7 @@ test_plane_position(data_t *data, enum pipe pipe, uint64_t tiling)
}
static void
-run_tests_for_pipe(data_t *data, enum pipe pipe)
+run_tests_for_pipe(data_t *data, enum pipe pipe, bool test_ddb)
{
igt_output_t *output;
@@ -334,15 +427,22 @@ run_tests_for_pipe(data_t *data, enum pipe pipe)
igt_require(data->display.pipes[pipe].n_planes > 0);
}
- igt_subtest_f("atomic-pipe-%s-tiling-x", kmstest_pipe_name(pipe))
+ data->flag = 0;
+ if (test_ddb)
+ data->flag = TEST_DDB_ALGO;
+
+ igt_subtest_f("atomic-pipe-%s-tiling-x%s", kmstest_pipe_name(pipe),
+ test_ddb ? "_ddb" : "")
for_each_valid_output_on_pipe(&data->display, pipe, output)
test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_X_TILED);
- igt_subtest_f("atomic-pipe-%s-tiling-y", kmstest_pipe_name(pipe))
+ igt_subtest_f("atomic-pipe-%s-tiling-y%s", kmstest_pipe_name(pipe),
+ test_ddb ? "_ddb" : "")
for_each_valid_output_on_pipe(&data->display, pipe, output)
test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_Y_TILED);
- igt_subtest_f("atomic-pipe-%s-tiling-yf", kmstest_pipe_name(pipe))
+ igt_subtest_f("atomic-pipe-%s-tiling-yf%s", kmstest_pipe_name(pipe),
+ test_ddb ? "_ddb" : "")
for_each_valid_output_on_pipe(&data->display, pipe, output)
test_plane_position(data, pipe, LOCAL_I915_FORMAT_MOD_Yf_TILED);
}
@@ -401,7 +501,9 @@ int main(int argc, char *argv[])
for_each_pipe_static(pipe) {
igt_subtest_group
- run_tests_for_pipe(&data, pipe);
+ run_tests_for_pipe(&data, pipe, false);
+ igt_subtest_group
+ run_tests_for_pipe(&data, pipe, true);
}
igt_fixture {
--
2.7.4
More information about the Intel-gfx
mailing list