[Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU) configuration to userspace
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Tue May 8 08:24:35 UTC 2018
On 08/05/2018 05:04, Rogozhkin, Dmitry V wrote:
>>> I'm pretty sure Dmitry wants dynamic configurations.
>
> Yes, I afraid we really need dynamic slice configurations for media.
Context of the question was whether you need to change slice
configuration for a single GEM context between submitting batch buffers?
Regards,
Tvrtko
> *From:*Landwerlin, Lionel G
> *Sent:* Friday, May 4, 2018 9:25 AM
> *To:* Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>;
> intel-gfx at lists.freedesktop.org; Rogozhkin, Dmitry V
> <dmitry.v.rogozhkin at intel.com>
> *Subject:* Re: [Intel-gfx] [PATCH 8/8] drm/i915: Expose RPCS (SSEU)
> configuration to userspace
>
> On 03/05/18 18:18, Tvrtko Ursulin wrote:
>
> +int intel_lr_context_set_sseu(struct i915_gem_context *ctx,
> + struct intel_engine_cs *engine,
> + struct i915_gem_context_sseu *sseu)
> +{
> + struct drm_i915_private *dev_priv = ctx->i915;
> + struct intel_context *ce;
> + enum intel_engine_id id;
> + int ret;
> +
> + lockdep_assert_held(&dev_priv->drm.struct_mutex);
> +
> + if (memcmp(sseu, &ctx->engine[engine->id].sseu,
> sizeof(*sseu)) == 0)
> + return 0;
> +
> + /*
> + * We can only program this on render ring.
> + */
> + ce = &ctx->engine[RCS];
> +
> + if (ce->pin_count) { /* Assume that the context is active! */
> + ret = i915_gem_switch_to_kernel_context(dev_priv);
> + if (ret)
> + return ret;
> +
> + ret = i915_gem_wait_for_idle(dev_priv,
> + I915_WAIT_INTERRUPTIBLE |
> + I915_WAIT_LOCKED);
>
>
> Could we consider the alternative of only allowing this to be
> configured on context create? That way we would not need to idle the
> GPU every time userspace decides to fiddle with it. It is
> unprivileged so quite an easy way for random app to ruin GPU
> performance for everyone.
>
> Regards,
>
> Tvrtko
>
> I'm pretty sure Dmitry wants dynamic configurations.
>
> Dmitry?
>
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