[Intel-gfx] [PATCH 04/11] drm/i915/icl: WaEnableFloatBlendOptimization

[Mika Kuoppala]

Oscar Mateo <oscar.mateo at intel.com> writes:

> Enables blend optimization for floating point RTs
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1406393558
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>

Let's see if we can get away without whitelisting this,
Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6e88c6b..f123c3e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2663,6 +2663,9 @@ enum i915_power_well_id {
>  #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
>  #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
>  
> +#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
> +#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
> +
>  #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
>  #define   GEN6_BLITTER_LOCK_SHIFT			16
>  #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 33a1a0c..e9c00b0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -479,6 +479,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>  		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>  				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
>  
> +	/* WaEnableFloatBlendOptimization:icl */
> +	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
> +
>  	return 0;
>  }
>  
> -- 
> 1.9.1