[Intel-gfx] [PATCH 5/7] drm/i915/guc: Refactoring preparation of the GUC_CTL_CTXINFO parameter

[Michal Wajdeczko]

On Wed, 30 May 2018 15:53:32 +0200, Piotr Piorkowski  
<piotr.piorkowski at intel.com> wrote:

> At the moment, the preparation of GUC_CTL_CTXINFO is disordered.
> Lets move all  GUC_CTL_CTXINFO related operations to one place.
>
> Signed-off-by: Piotr Piórkowski <piotr.piorkowski at intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Michał Winiarski <michal.winiarski at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_guc.c | 30 ++++++++++++++++++++----------
>  1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c  
> b/drivers/gpu/drm/i915/intel_guc.c
> index 185459ee49c9..3b45f06b1aa2 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -239,6 +239,25 @@ static u32 guc_ctl_feature_flags(struct intel_guc  
> *guc)
> 	return flags;
>  }
> +
> +static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
> +{
> +	u32 flags = 0;
> +	u32 ctxnum;
> +	u32 base;

better to declare ctxnum/base inside 'if' below

> +
> +	if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
> +
> +		base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
> +		ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
> +
> +		base >>= PAGE_SHIFT;
> +		flags = (base << GUC_CTL_BASE_ADDR_SHIFT) |

to be future friendly and not overwrite other bits use:

		flags |= ...

> +			(ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
> +	}
> +	return flags;
> +}
> +
>  static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>  {
>  	u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
> @@ -280,16 +299,7 @@ void intel_guc_init_params(struct intel_guc *guc)
>  	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
>  	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
>  	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
> -
> -	/* If GuC submission is enabled, set up additional parameters here */
> -	if (USES_GUC_SUBMISSION(dev_priv)) {
> -		u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
> -		u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
> -
> -		pgs >>= PAGE_SHIFT;
> -		params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
> -			(ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
> -	}
> +	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
> 	/*
>  	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and

with above fixed,

Reviewed-by: Michal Wajdeczko <michal.wajdeczko at intel.com>