[Intel-gfx] [PATCH v7 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC

[Ville Syrjälä]

On Thu, Nov 01, 2018 at 11:46:58PM -0700, Manasi Navare wrote:
> A separate power well 2 (PG2) is required for VDSC on eDP transcoder
> whereas all other transcoders use the power wells associated with the
> transcoders for VDSC.
> This patch adds a helper to obtain correct power domain depending on
> transcoder being used and enables/disables the power wells during
> VDSC enabling/disabling.
> 
> v3:
> * Call it intel_dsc_power_domain, add to
> intel_ddi_get_power_domains (Ville)
> v2:
> * Fix tabs, const crtc_state, fix comments (Ville)
> 
> Suggested-by: Ville Syrjala <ville.syrjala at linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c  |  3 ++-
>  drivers/gpu/drm/i915/intel_drv.h  |  2 ++
>  drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++
>  3 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index af12c15ed94f..c243bb3f2be9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2124,7 +2124,8 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state) ||
>  	    intel_port_is_tc(dev_priv, encoder->port))
> -		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));
> +		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port)) |
> +			BIT_ULL(intel_dsc_power_domain(crtc_state));

if (crtc_state->something)
	domains |= ...;

>  
>  	return domains;
>  }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e537561b3d40..2d41dff6eed1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1859,6 +1859,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
>  /* intel_vdsc.c */
>  int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config);
> +enum intel_display_power_domain
> +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
>  
>  static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> index 219dc1517c8a..9eae037a3b4d 100644
> --- a/drivers/gpu/drm/i915/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/intel_vdsc.c
> @@ -581,6 +581,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +enum intel_display_power_domain
> +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> +{
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	/*
> +	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
> +	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> +	 * For any other transcoder, VDSC/joining uses the power well associated
> +	 * with the pipe/transcoder in use. Hence another reference on the
> +	 * transcoder power domain will suffice.
> +	 */
> +	if (cpu_transcoder == TRANSCODER_EDP)
> +		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> +	else
> +		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> +}
> +
>  static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
>  						const struct intel_crtc_state *crtc_state)
>  {
> @@ -1020,6 +1038,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
>  	if (!crtc_state->dsc_params.compression_enable)
>  		return;
>  
> +	/* Enable Power wells for VDSC/joining */
> +	intel_display_power_get(dev_priv,
> +				intel_dsc_power_domain(crtc_state));
> +
>  	intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
>  
>  	intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
> @@ -1072,4 +1094,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
>  				  RIGHT_BRANCH_VDSC_ENABLE);
>  	I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
>  
> +	/* Disable Power wells for VDSC/joining */
> +	intel_display_power_put(dev_priv,
> +				intel_dsc_power_domain(old_crtc_state));
>  }
> -- 
> 2.18.0

-- 
Ville Syrjälä
Intel