[Intel-gfx] [PATCH 2/2] drm/i915/icl: Configure MG DP mode for HDMI ports too
Souza, Jose
jose.souza at intel.com
Fri Nov 2 21:54:55 UTC 2018
On Fri, 2018-11-02 at 21:26 +0200, Imre Deak wrote:
> The MG DP mode needs to be configured for Type C static/fixed/legacy
> HDMI ports too, the same way as it's configured for Type C
> static/fixed/legacy, fix this.
Reviewed-by: José Roberto de Souza <jose.souza at intel.com>
>
> Bspec: 4232, 21735
> Cc: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 68
> +++++++++++++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_dp.c | 66 ------------------------------
> --------
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> 3 files changed, 67 insertions(+), 68 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index cb06058179fd..ab9a36c4ba3b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2980,6 +2980,71 @@ static void
> icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
> I915_WRITE(MG_MISC_SUS0(tc_port), val);
> }
>
> +static void icl_program_mg_dp_mode(struct intel_digital_port
> *intel_dig_port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_dig_port-
> >base.base.dev);
> + enum port port = intel_dig_port->base.port;
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 ln0, ln1, lane_info;
> +
> + if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type ==
> TC_PORT_TBT)
> + return;
> +
> + ln0 = I915_READ(MG_DP_MODE(port, 0));
> + ln1 = I915_READ(MG_DP_MODE(port, 1));
> +
> + switch (intel_dig_port->tc_type) {
> + case TC_PORT_TYPEC:
> + ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> + ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> +
> + lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> + DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> + DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> +
> + switch (lane_info) {
> + case 0x1:
> + case 0x4:
> + break;
> + case 0x2:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0x3:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0x8:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> + break;
> + case 0xC:
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + case 0xF:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> + MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> + default:
> + MISSING_CASE(lane_info);
> + }
> + break;
> +
> + case TC_PORT_LEGACY:
> + ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> + ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> + break;
> +
> + default:
> + MISSING_CASE(intel_dig_port->tc_type);
> + return;
> + }
> +
> + I915_WRITE(MG_DP_MODE(port, 0), ln0);
> + I915_WRITE(MG_DP_MODE(port, 1), ln1);
> +}
> +
> static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state,
> const struct drm_connector_state
> *conn_state)
> @@ -3002,7 +3067,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> - icl_program_mg_dp_mode(intel_dp);
> + icl_program_mg_dp_mode(dig_port);
> icl_disable_phy_clock_gating(dig_port);
>
> if (IS_ICELAKE(dev_priv))
> @@ -3044,6 +3109,7 @@ static void intel_ddi_pre_enable_hdmi(struct
> intel_encoder *encoder,
>
> intel_display_power_get(dev_priv, dig_port-
> >ddi_io_power_domain);
>
> + icl_program_mg_dp_mode(dig_port);
> icl_disable_phy_clock_gating(dig_port);
>
> if (IS_ICELAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index 127fc82902c6..b667fa85f609 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -241,72 +241,6 @@ intel_dp_link_required(int pixel_clock, int bpp)
> return DIV_ROUND_UP(pixel_clock * bpp, 8);
> }
>
> -void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
> -{
> - struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - enum port port = intel_dig_port->base.port;
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> - u32 ln0, ln1, lane_info;
> -
> - if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type ==
> TC_PORT_TBT)
> - return;
> -
> - ln0 = I915_READ(MG_DP_MODE(port, 0));
> - ln1 = I915_READ(MG_DP_MODE(port, 1));
> -
> - switch (intel_dig_port->tc_type) {
> - case TC_PORT_TYPEC:
> - ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> - ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE);
> -
> - lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
> - DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
> - DP_LANE_ASSIGNMENT_SHIFT(tc_port);
> -
> - switch (lane_info) {
> - case 0x1:
> - case 0x4:
> - break;
> - case 0x2:
> - ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
> - break;
> - case 0x3:
> - ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> - MG_DP_MODE_CFG_DP_X2_MODE;
> - break;
> - case 0x8:
> - ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> - break;
> - case 0xC:
> - ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> - MG_DP_MODE_CFG_DP_X2_MODE;
> - break;
> - case 0xF:
> - ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> - MG_DP_MODE_CFG_DP_X2_MODE;
> - ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> - MG_DP_MODE_CFG_DP_X2_MODE;
> - break;
> - default:
> - MISSING_CASE(lane_info);
> - }
> - break;
> -
> - case TC_PORT_LEGACY:
> - ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> - ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
> MG_DP_MODE_CFG_DP_X2_MODE;
> - break;
> -
> - default:
> - MISSING_CASE(intel_dig_port->tc_type);
> - return;
> - }
> -
> - I915_WRITE(MG_DP_MODE(port, 0), ln0);
> - I915_WRITE(MG_DP_MODE(port, 1), ln1);
> -}
> -
> int
> intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index d0be59599e23..a0f90d684a6b 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1819,7 +1819,6 @@ void intel_edp_drrs_invalidate(struct
> drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
> unsigned int frontbuffer_bits);
> -void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
>
> void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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