[Intel-gfx] [PATCH] drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IA

[Chris Wilson]

Quoting Mika Kuoppala (2018-11-09 13:56:52)
> This got duplicated on introducing icl workarounds.
> Fix by using the older definition and moving the wa bit
> definition there. No functional changes.
> 
> Fixes: 908ae0517363 ("drm/i915/icl: WaDisCtxReload")

But worth backporting for no functional change? Maybe just References:

> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 4 +---
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 ++--
>  2 files changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 158cf4716d03..68f7e8a42258 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2400,6 +2400,7 @@ enum i915_power_well_id {
>  
>  #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080)
>  #define   GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF
> +#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE      (1 << 7)
>  
>  #define GAMT_CHKN_BIT_REG      _MMIO(0x4ab8)
>  #define   GAMT_CHKN_DISABLE_L3_COH_PIPE                        (1 << 31)
> @@ -8708,9 +8709,6 @@ enum {
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC     (1 << 9)
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC      (1 << 7)
>  
> -#define GAMW_ECO_DEV_RW_IA_REG                 _MMIO(0x4080)
> -#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE      (1 << 7)
> -
>  #define GEN10_SAMPLER_MODE             _MMIO(0xE18C)
>  
>  /* IVYBRIDGE DPF */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index d7176213e3ce..37a7276926d9 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -867,8 +867,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>         /* Wa_220166154:icl
>          * Formerly known as WaDisCtxReload
>          */
> -       I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
> -                                          GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
> +       I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
> +                  GAMW_ECO_DEV_CTX_RELOAD_DISABLE);

What happened? I had this file all nicely aligned. And then icl polluted
it again. Please remember the visual grouping.

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris