[Intel-gfx] [PATCH] drm/i915/glk: Use cached RCOMP value when re-enabling DPIO Phy

[Imre Deak]

On Thu, Nov 15, 2018 at 11:48:06AM -0800, clinton.a.taylor at intel.com wrote:
> From: Clint Taylor <clinton.a.taylor at intel.com>
> 
> The calibration RCOMP value in PORT_TX_DW6 in stored in dev_priv during
> driver init. Use this value instead of reading the register again as the
> power well for PORTA RCOMP register may not be enabled and will return
> 0xFFFFFFFF instead of the computed value.

PORT_REF_DW6 for both the port A and the port B/C PHYs are in power well
#0, which is always on whenever we are runtime resumed (which is always
the case during _bxt_ddi_phy_init). Also the PHY for port A always gets
enabled before we read out the comp value.

What are the other port A PHY registers in the above case?

Could it be that the port A PHY power gating in PORT_CL1CM_DW28 causes
this?

Not sure how good it is to reuse the same comp value across multiple
off/on cycles, it could change in theory. There could also be some other
issue with the port A PHY init.

> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index 3c7f10d..7cee57f 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -422,8 +422,12 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  		 * the corresponding calibrated value from PHY1, and disable
>  		 * the automatic calibration on PHY0.
>  		 */
> -		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> -							  phy_info->rcomp_phy);
> +		if (!dev_priv->bxt_phy_grc)
> +			val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
> +								  phy_info->rcomp_phy);
> +		else
> +			val = dev_priv->bxt_phy_grc;
> +
>  		grc_code = val << GRC_CODE_FAST_SHIFT |
>  			   val << GRC_CODE_SLOW_SHIFT |
>  			   val;
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx