[Intel-gfx] [PATCH] drm/i915/cnl: Fix the formulae for register offsets

[Jani Nikula]

On Fri, 23 Nov 2018, Radhakrishna Sripada <radhakrishna.sripada at intel.com> wrote:
> For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices.

Maybe it's time to realize using calculations like this isn't viable
anymore. For a seemingly simple change like this, I think it just takes
too long to review. It just underlines my point that the original was
wrong already.

There macros aren't widely used. Despite the large number of slices, I'd
go for explicitly defining the per-slice registers and using _PICK() to
choose.

BR,
Jani.



>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 47baf2fe8f71..352024756e91 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8662,18 +8662,21 @@ enum {
>  #define   CHV_EU311_PG_ENABLE		(1 << 1)
>  
>  #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice) * 0x4)
> -#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * 0x34 + \
> -					      ((slice) % 3) * 0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x34 : 0x2C) \
> +					      + ((slice) % 3) * 0x4)
>  #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>  #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice) * 2))
>  #define   GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F)
>  
>  #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice) * 0x8)
> -#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * 0x30 + \
> -					      ((slice) % 3) * 0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
> +					      + ((slice) % 3) * 0x8)
>  #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice) * 0x8)
> -#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * 0x30 + \
> -					      ((slice) % 3) * 0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + ((slice) / 3) * \
> +					      ((((slice) / 3) == 1) ? 0x30 : 0x28) \
> +					      + ((slice) % 3) * 0x8)
>  #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
>  #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
>  #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)

-- 
Jani Nikula, Intel Open Source Graphics Center