[Intel-gfx] [PATCH 2/3] drm/i915: Allocate a common scratch page

[Chris Wilson]

Quoting Mika Kuoppala (2018-11-28 13:21:41)
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 08fd9b12e4d7..3464058cbfc7 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1281,7 +1281,7 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
> >  {
> >       *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
> >       *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
> > -     *batch++ = i915_ggtt_offset(engine->scratch) + 256;
> > +     *batch++ = i915_ggtt_offset(engine->i915->gt.scratch) + 256;
> 
> How do we get away with these rmws? Because we only have one render engine
> or that we sync after each engine init?

We get away with it because it's the only engine in this gen using this
dword. We can make it more official by marking reserved portions of the
scratch page.

Why is L3SQCREG4 whitelisted? mesa doesn't seem to be using it.
-Chris