[Intel-gfx] [PATCH 1/3] drm/fourcc: Add 64 bpp half float formats
Strasser, Kevin
kevin.strasser at intel.com
Thu Nov 29 21:38:12 UTC 2018
Ville Syrjälä wrote:
> On Wed, Nov 28, 2018 at 10:38:11PM -0800, Kevin Strasser wrote:
>> + { .format = DRM_FORMAT_XRGB16161616H, .depth = 48, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true },
>> + { .format = DRM_FORMAT_XBGR16161616H, .depth = 48, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_fp = true },
>> + { .format = DRM_FORMAT_ARGB16161616H, .depth = 64, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_fp = true },
>> + { .format = DRM_FORMAT_ABGR16161616H, .depth = 64, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_fp = true },
>
> cpp is wrong for all of these.
I'll change it to .cpp = { 8, 0, 0 }
>> +/* 64 bpp RGB IEEE-754 half-precision float (binary16) */
>
> Might as well document the bits:
> * [15:0] sign:exponent:mantissa 1:5:10
Sure.
>> +#define DRM_FORMAT_XBGR16161616H fourcc_code('X', 'B', '4', 'H') /* [63:0] >> x:B:G:R 16:16:16:16 little endian */
>> +#define DRM_FORMAT_ABGR16161616H fourcc_code('A', 'B', '4', 'H') /* [63:0] >> A:B:G:R 16:16:16:16 little endian */
>> +#define DRM_FORMAT_XRGB16161616H fourcc_code('X', 'R', '4', 'H') /* [63:0] >> x:R:G:B 16:16:16:16 little endian */
>> +#define DRM_FORMAT_ARGB16161616H fourcc_code('A', 'R', '4', 'H') /* [63:0] >> A:R:G:B 16:16:16:16 little endian */
>
> ocd: the other formats have separate groups for X vs. A separate.
> And RGB before BGR.
Agreed, I'll fix these up.
Thanks,
Kevin
More information about the Intel-gfx
mailing list