[Intel-gfx] [PATCH v2] drm/i915: Pipeline PDP updates for Braswell

[kbuild test robot]

Hi Chris,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20181129]
[cannot apply to v4.20-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Pipeline-PDP-updates-for-Braswell/20181129-054757
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/i915/intel_lrc.c:1852:50: error: no member 'scratch' in struct <unnamed>
   include/linux/slab.h:332:43: warning: dubious: x & !y
   drivers/gpu/drm/i915/intel_lrc.c: In function 'emit_pdps':
   drivers/gpu/drm/i915/intel_lrc.c:1852:43: error: 'struct <anonymous>' has no member named 'scratch'
     *cs++ = i915_ggtt_offset(engine->i915->gt.scratch);
                                              ^

vim +/scratch +1852 drivers/gpu/drm/i915/intel_lrc.c

  1808	
  1809	static int emit_pdps(struct i915_request *rq)
  1810	{
  1811		const struct intel_engine_cs * const engine = rq->engine;
  1812		struct i915_hw_ppgtt * const ppgtt = rq->gem_context->ppgtt;
  1813		const unsigned int num_rings = INTEL_INFO(rq->i915)->num_rings;
  1814		struct intel_engine_cs *other;
  1815		enum intel_engine_id id;
  1816		u32 *cs;
  1817		int i;
  1818	
  1819		if (!(ppgtt->pd_dirty_rings & intel_engine_flag(engine)))
  1820			return 0;
  1821	
  1822		cs = intel_ring_begin(rq, 4 * (GEN8_3LVL_PDPES + num_rings) + 8);
  1823		if (IS_ERR(cs))
  1824			return PTR_ERR(cs);
  1825	
  1826		/*
  1827		 * Force the GPU (not just the local engine/powerwell!) to remain awake,
  1828		 * or else we may kill the machine with "timed out waiting for
  1829		 * forcewake ack request".
  1830		 */
  1831	
  1832		*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
  1833		for_each_engine(other, rq->i915, id) {
  1834			*cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base));
  1835			*cs++ = _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
  1836		}
  1837	
  1838		*cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES);
  1839		for (i = GEN8_3LVL_PDPES; i--; ) {
  1840			const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
  1841	
  1842			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
  1843			*cs++ = upper_32_bits(pd_daddr);
  1844			*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
  1845			*cs++ = lower_32_bits(pd_daddr);
  1846		}
  1847		*cs++ = MI_NOOP;
  1848	
  1849		/* Posting read to flush the mmio before letting the GPU sleep again */
  1850		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
  1851		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0));
> 1852		*cs++ = i915_ggtt_offset(engine->i915->gt.scratch);
  1853		*cs++ = 0;
  1854	
  1855		*cs++ = MI_LOAD_REGISTER_IMM(num_rings);
  1856		for_each_engine(other, rq->i915, id) {
  1857			*cs++ = i915_mmio_reg_offset(RING_PSMI_CTL(other->mmio_base));
  1858			*cs++ = _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE);
  1859		}
  1860	
  1861		intel_ring_advance(rq, cs);
  1862	
  1863		ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
  1864		return 0;
  1865	}
  1866	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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