[Intel-gfx] [PATCH v11 20/23] drm/i915/icl: add pll mapping for DSI

[Madhav Chauhan]

On 11/29/2018 7:42 PM, Jani Nikula wrote:
> Add encoder specific pll mapping for DSI. The differences with the DDI
> version are big enough to warrant a separate function.
>
> Cc: Madhav Chauhan <madhav.chauhan at intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>   drivers/gpu/drm/i915/icl_dsi.c | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index e3aa9d3d2291..1907640a2e6a 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -570,6 +570,27 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
>   	mutex_unlock(&dev_priv->dpll_lock);
>   }
>   
> +static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> +			      const struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> +	enum port port;
> +	u32 val;
> +
> +	mutex_lock(&dev_priv->dpll_lock);
> +
> +	val = I915_READ(DPCLKA_CFGCR0_ICL);
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> +	}
> +	I915_WRITE(DPCLKA_CFGCR0_ICL, val);

We need to read back  DPCLKA_CFGCR0_ICL to ensure write completed before 
next step as per BSPEC.
With this fix,
Reviewed-by: Madhav Chauhan <madhav.chauhan at intel.com>

Regards,
Madhav

> +
> +	mutex_unlock(&dev_priv->dpll_lock);
> +}
> +
>   static void
>   gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>   			       const struct intel_crtc_state *pipe_config)
> @@ -978,6 +999,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
>   {
>   	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>   
> +	/* step3b */
> +	gen11_dsi_map_pll(encoder, pipe_config);
/* step4: enable DSI port and DPHY */
>   	gen11_dsi_enable_port_and_phy(encoder, pipe_config);
>