[Intel-gfx] [PATCH 5/8] drm/i915/icl: Refactor icl pll functions

[Lucas De Marchi]

On Wed, Oct 03, 2018 at 12:52:00PM +0530, Mahesh Kumar wrote:
> From: Vandita Kulkarni <vandita.kulkarni at intel.com>
> 
> This patch adds helper function for identifying
> whether the given PLL is combo PHY PLL or not.
> This helper function is used inside various ICL
> functions to make them scalable.
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
> Cc: Madhav Chauhan <madhav.chauhan at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

> ---
>  drivers/gpu/drm/i915/intel_display.c  |  2 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 54 +++++++++++------------------------
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
>  3 files changed, 19 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e31d71526afd..a1c6891cf14b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9301,7 +9301,7 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
>  		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>  		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>  
> -		if (WARN_ON(id != DPLL_ID_ICL_DPLL0 && id != DPLL_ID_ICL_DPLL1))
> +		if (WARN_ON(!intel_dpll_is_combophy(id)))
>  			return;
>  	} else if (intel_port_is_tc(dev_priv, port)) {
>  		id = icl_port_to_mg_pll_id(port);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 5b2ee49aee14..93e8e2307989 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2633,6 +2633,11 @@ enum intel_dpll_id icl_port_to_mg_pll_id(enum port port)
>  	return port - PORT_C + DPLL_ID_ICL_MGPLL1;
>  }
>  
> +bool intel_dpll_is_combophy(enum intel_dpll_id id)
> +{
> +	return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
> +}
> +
>  static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  				     uint32_t *target_dco_khz,
>  				     struct intel_dpll_hw_state *state)
> @@ -2926,21 +2931,16 @@ icl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>  
>  static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
>  {
> -	switch (id) {
> -	default:
> -		MISSING_CASE(id);
> -		/* fall through */
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> +	if (intel_dpll_is_combophy(id))
>  		return CNL_DPLL_ENABLE(id);
> -	case DPLL_ID_ICL_TBTPLL:
> +	else if (id == DPLL_ID_ICL_TBTPLL)
>  		return TBT_PLL_ENABLE;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	else
> +		/*
> +		 * TODO: Make MG_PLL macros use
> +		 * tc port id instead of port id
> +		 */
>  		return MG_PLL_ENABLE(icl_mg_pll_id_to_port(id));
> -	}
>  }
>  
>  static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -2959,17 +2959,11 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PLL_ENABLE))
>  		goto out;
>  
> -	switch (id) {
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> -	case DPLL_ID_ICL_TBTPLL:
> +	if (intel_dpll_is_combophy(id) ||
> +	    id == DPLL_ID_ICL_TBTPLL) {
>  		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>  		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> -		break;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	} else {
>  		port = icl_mg_pll_id_to_port(id);
>  		hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(port));
>  		hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
> @@ -3007,9 +3001,6 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  
>  		hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
>  		hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
> -		break;
> -	default:
> -		MISSING_CASE(id);
>  	}
>  
>  	ret = true;
> @@ -3098,21 +3089,10 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
>  				    PLL_POWER_STATE, 1))
>  		DRM_ERROR("PLL %d Power not enabled\n", id);
>  
> -	switch (id) {
> -	case DPLL_ID_ICL_DPLL0:
> -	case DPLL_ID_ICL_DPLL1:
> -	case DPLL_ID_ICL_TBTPLL:
> +	if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
>  		icl_dpll_write(dev_priv, pll);
> -		break;
> -	case DPLL_ID_ICL_MGPLL1:
> -	case DPLL_ID_ICL_MGPLL2:
> -	case DPLL_ID_ICL_MGPLL3:
> -	case DPLL_ID_ICL_MGPLL4:
> +	else
>  		icl_mg_pll_write(dev_priv, pll);
> -		break;
> -	default:
> -		MISSING_CASE(id);
> -	}
>  
>  	/*
>  	 * DVFS pre sequence would be here, but in our driver the cdclk code
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 5305ce1c2175..6a79ced923e9 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -346,5 +346,6 @@ int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>  			       uint32_t pll_id);
>  int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
>  enum intel_dpll_id icl_port_to_mg_pll_id(enum port port);
> +bool intel_dpll_is_combophy(enum intel_dpll_id id);
>  
>  #endif /* _INTEL_DPLL_MGR_H_ */
> -- 
> 2.16.2
> 
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