[Intel-gfx] [PATCH v2 6/6] drm/i915/icl:Add Wa_1606682166

[Mika Kuoppala]

Radhakrishna Sripada <radhakrishna.sripada at intel.com> writes:

> From: Anuj Phogat <anuj.phogat at gmail.com>
>
> Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
> Disable the Sampler state prefetch functionality in the SARB by
> programming 0xB000[30] to '1'. This is to be done at boot time
> and the feature must remain disabled permanently.
>
> Fixes flaky tex-mip-level-selection* piglit tests with Mesa i965
> driver.
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>

Pushed to dinq, thanks for the patch.
-Mika

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_workarounds.c | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa020425754f..0c544161ed47 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7415,6 +7415,7 @@ enum {
>  
>  #define GEN7_SARCHKMD				_MMIO(0xB000)
>  #define GEN7_DISABLE_DEMAND_PREFETCH		(1 << 31)
> +#define GEN7_DISABLE_SAMPLER_PREFETCH           (1 << 30)
>  
>  #define GEN7_L3SQCREG1				_MMIO(0xB010)
>  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index cf4f4c1f86ab..7157115e5bc9 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -910,7 +910,8 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
>  		I915_WRITE(GEN7_SARCHKMD,
>  			   I915_READ(GEN7_SARCHKMD) |
> -			   GEN7_DISABLE_DEMAND_PREFETCH);
> +			   GEN7_DISABLE_DEMAND_PREFETCH |
> +			   GEN7_DISABLE_SAMPLER_PREFETCH);
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 2.9.3
>
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