[Intel-gfx] [PATCH 3/6] drm/i915: fix the watermark result selection on glk/gen10+

[Matt Roper]

On Tue, Oct 09, 2018 at 04:55:15PM -0700, Matt Roper wrote:
> On Thu, Oct 04, 2018 at 04:15:57PM -0700, Paulo Zanoni wrote:
> > On these platforms we're supposed to unconditonally pick the method 2
> > result instead of the minimum.
> 
> In addition to this, it looks like the calculations for method 1 and
> method 2 need a slight update.  gen10/gen11 adds an extra "+1" to the
> end of the method1 calculation and also to the interm_pbpl used in
> various method 2 calculations.
> 

Actually, it looks like you've already made these updates in a previous
patch; disregard this comment.

The rest of this patch looks good.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> 
> Matt
> 
> > 
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++-------
> >  1 file changed, 16 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index cab86690a0ba..40ce99c455f3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4672,15 +4672,24 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> >  	} else {
> >  		if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
> >  		     wp->dbuf_block_size < 1) &&
> > -		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1))
> > +		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> >  			selected_result = method2;
> > -		else if (ddb_allocation >=
> > -			 fixed16_to_u32_round_up(wp->plane_blocks_per_line))
> > -			selected_result = min_fixed16(method1, method2);
> > -		else if (latency >= wp->linetime_us)
> > -			selected_result = min_fixed16(method1, method2);
> > -		else
> > +		} else if (ddb_allocation >=
> > +			 fixed16_to_u32_round_up(wp->plane_blocks_per_line)) {
> > +			if (INTEL_GEN(dev_priv) == 9 &&
> > +			    !IS_GEMINILAKE(dev_priv))
> > +				selected_result = min_fixed16(method1, method2);
> > +			else
> > +				selected_result = method2;
> > +		} else if (latency >= wp->linetime_us) {
> > +			if (INTEL_GEN(dev_priv) == 9 &&
> > +			    !IS_GEMINILAKE(dev_priv))
> > +				selected_result = min_fixed16(method1, method2);
> > +			else
> > +				selected_result = method2;
> > +		} else {
> >  			selected_result = method1;
> > +		}
> >  	}
> >  
> >  	res_blocks = fixed16_to_u32_round_up(selected_result) + 1;
> > -- 
> > 2.14.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795