[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
Patchwork
patchwork at emeril.freedesktop.org
Thu Oct 11 06:32:03 UTC 2018
== Series Details ==
Series: series starting with [v1,01/10] drm/i915: introduced pv capability for vgpu
URL : https://patchwork.freedesktop.org/series/50851/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
aeb1adffcb63 drm/i915: introduced pv capability for vgpu
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level) \
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'level' may be better as '(level)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level) \
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
-:58: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#58: FILE: drivers/gpu/drm/i915/i915_drv.h:3890:
+ (intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+ && (dev_priv->vgpu.pv_caps & level))
-:138: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#138: FILE: drivers/gpu/drm/i915/i915_vgpu.c:91:
+ __raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+ dev_priv->vgpu.pv_caps);
-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/i915/i915_vgpu.c:93:
+ dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+ vgtif_reg(enable_pvmmio));
-:143: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#143: FILE: drivers/gpu/drm/i915/i915_vgpu.c:96:
+ DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+ dev_priv->vgpu.pv_caps);
total: 0 errors, 0 warnings, 6 checks, 103 lines checked
317678bb037d drm/i915: get ready of memory for pvmmio
-:50: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:1348:
+ spinlock_t shared_page_lock;
-:124: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#124: FILE: drivers/gpu/drm/i915/i915_vgpu.c:104:
+ __raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+ lower_32_bits(shared_page_gpa));
-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/i915_vgpu.c:106:
+ __raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+ upper_32_bits(shared_page_gpa));
total: 0 errors, 0 warnings, 3 checks, 92 lines checked
1dde34d63842 drm/i915: context submission pvmmio optimization
18b5f4aa055d drm/i915: master irq pvmmio optimization
14033ac83189 drm/i915: ppgtt update pvmmio optimization
657a3ae6fb1e drm/i915/gvt: GVTg handle enable_pvmmio PVINFO register
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1249:
+ DRM_INFO("vgpu id=%d pvmmio=0x%x\n",
+ vgpu->id, VGPU_PVMMIO(vgpu));
total: 0 errors, 0 warnings, 1 checks, 53 lines checked
3e9412478d43 drm/i915/gvt: GVTg read_shared_page implementation
-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/gvt/gvt.h:695:
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len);
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/gvt/handlers.c:1257:
+ vgpu->shared_page_gpa = vgpu_vreg64_t(vgpu,
+ vgtif_reg(shared_page_gpa));
-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/gvt/vgpu.c:599:
+void intel_gvt_read_shared_page(struct intel_vgpu *vgpu,
+ unsigned int offset, void *buf, unsigned long len)
total: 0 errors, 0 warnings, 3 checks, 44 lines checked
4e2a15c60584 drm/i915/gvt: GVTg support context submission pvmmio optimization
4cb1532b4851 drm/i915/gvt: GVTg support master irq pvmmio optimization
7ff85a910ce0 drm/i915/gvt: GVTg support ppgtt pvmmio optimization
-:77: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#77: FILE: drivers/gpu/drm/i915/gvt/gtt.c:1810:
+ gvt_vgpu_err("fail to create ppgtt for pdp 0x%llx\n",
+ px_dma(&mm->ppgtt->pml4));
-:107: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#107: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2819:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:132: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#132: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2844:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:160: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#160: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2872:
+#define pml4_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PML4E_SIZE) & GEN8_PML4E_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:166: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#166: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2878:
+#define pdp_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PDPE_SIZE) & GEN8_PDPE_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:172: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'end' - possible side-effects?
#172: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2884:
+#define pd_addr_end(addr, end) \
+({ unsigned long __boundary = \
+ ((addr) + GEN8_PDE_SIZE) & GEN8_PDE_SIZE_MASK; \
+ (__boundary < (end)) ? __boundary : (end); \
+})
-:185: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#185: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2897:
+static int walk_pt_range(struct intel_vgpu *vgpu, u64 pt,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:198: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#198: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2910:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pt & PAGE_MASK) + (start_index << info->gtt_entry_size_shift),
-:219: CHECK:LINE_SPACING: Please don't use multiple blank lines
#219: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2931:
+
+
-:221: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#221: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2933:
+static int walk_pd_range(struct intel_vgpu *vgpu, u64 pd,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:233: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#233: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2945:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pd & PAGE_MASK) + (index <<
-:246: CHECK:LINE_SPACING: Please don't use multiple blank lines
#246: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2958:
+
+
-:248: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#248: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2960:
+static int walk_pdp_range(struct intel_vgpu *vgpu, u64 pdp,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#260: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2972:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pdp & PAGE_MASK) + (index <<
-:272: CHECK:LINE_SPACING: Please don't use multiple blank lines
#272: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2984:
+
+
-:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#274: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2986:
+static int walk_pml4_range(struct intel_vgpu *vgpu, u64 pml4,
+ u64 start, u64 end, struct ppgtt_walk *walk)
-:285: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#285: FILE: drivers/gpu/drm/i915/gvt/gtt.c:2997:
+ ret = intel_gvt_hypervisor_read_gpa(vgpu,
+ (pml4 & PAGE_MASK) + (index <<
-:298: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#298: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3010:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[])
-:332: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#332: FILE: drivers/gpu/drm/i915/gvt/gtt.c:3044:
+ walk.mfns = kmalloc_array(num_pages,
+ sizeof(unsigned long), GFP_KERNEL);
-:392: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#392: FILE: drivers/gpu/drm/i915/gvt/gtt.h:277:
+int intel_vgpu_g2v_pv_ppgtt_alloc_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
-:395: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#395: FILE: drivers/gpu/drm/i915/gvt/gtt.h:280:
+int intel_vgpu_g2v_pv_ppgtt_clear_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
-:398: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#398: FILE: drivers/gpu/drm/i915/gvt/gtt.h:283:
+int intel_vgpu_g2v_pv_ppgtt_insert_4lvl(struct intel_vgpu *vgpu,
+ u64 pdps[]);
total: 0 errors, 0 warnings, 22 checks, 395 lines checked
More information about the Intel-gfx
mailing list