[Intel-gfx] [PATCH 3/3] drm/i915/guc: sleep on enable

[Daniele Ceraolo Spurio]

On 14/10/18 10:02, Chris Wilson wrote:
> Seems like there's a missing ack before the guc is ready for commands.
> 

I'm assuming you're running without HuC since the HuC auth H2G comes 
before this one.
What we're polling to indicate load completion (GS_UKERNEL_READY) is 
definitely what the firmware uses to signal readiness. The other check 
we do (GS_MIA_CORE_STATE) should only apply for rc6 scenarios. From what 
I can see from the firmware code, all the initialization steps are done 
before GS_UKERNEL_READY is written to the status register so there 
shouldn't be any missing acks in principle.
Is the GuC returning anything in the scratch 0 register? It should be 
printed out by the H2G error message. The value of the status register 
(0xc000) could also provide interesting debug info.

Thanks,
Daniele

> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_submission.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index fb0499f80b62..b7fd3422cb28 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -1307,6 +1307,8 @@ int intel_guc_submission_enable(struct intel_guc *guc)
>   
>   	GEM_BUG_ON(!guc->execbuf_client);
>   
> +	usleep_range(1000, 10000);
> +
>   	err = intel_guc_sample_forcewake(guc);
>   	if (err)
>   		return err;
>