[Intel-gfx] [PATCH 03/11] drm/i915: fix handling of invisible planes in watermarks code

[Paulo Zanoni]

Before the patch, if a plane was not visible,
skl_compute_plane_wm_params() would return early without writing
anything to the wm_params struct. This would leave garbage in the
struct since it is not previously zeroed, and then we would later
check for wm_params.is_planar, which could be true due to the usage of
uninitialized memory. This would lead us to calculate the zeroed
watermarks for the second inexistent plane and mark the plane as a
planar plane. Then later this check would affect our decisions in
skl_write_plane_wm().

I can't see how this would lead to a noticeable bug in our code, but
it leads us to calculate watermarks for every level + transition
watermarks, twice (due to the is_planar bug). So the fix saves us a
lot of instructions.

This problem was found when I decided to add a DRM_ERROR for the
currently unsupported planar formats on ICL: kms_cursor_legacy would
trigger the error message without using planar formats.

So the fix we adopt in this patch is to create a new watermark
parameter called plane_visible and use it to avoid computing the
watermarks for invisible planes later. We also remove the checks that
are now made redundant by it.

Testcase: igt/kms_cursor_legacy/nonblocking-modeset-vs-cursor-atomic
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 ++++++---------
 2 files changed, 7 insertions(+), 9 deletions(-)

The error message mentioned above isd the one added by patch 06 of the
series.

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3616b718b5d2..4b1e8471609b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1250,6 +1250,7 @@ struct skl_wm_level {
 
 /* Stores plane specific WM parameters */
 struct skl_wm_params {
+	bool plane_visible;
 	bool x_tiled, y_tiled;
 	bool rc_surface;
 	bool is_planar;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 18157c6ee126..9043ffe40ce8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4532,7 +4532,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		to_intel_atomic_state(cstate->base.state);
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 
-	if (!intel_wm_plane_visible(cstate, intel_pstate))
+	wp->plane_visible = intel_wm_plane_visible(cstate, intel_pstate);
+	if (!wp->plane_visible)
 		return 0;
 
 	/* only NV12 format has two planes */
@@ -4645,8 +4646,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
 	uint32_t min_disp_buf_needed;
 
-	if (latency == 0 ||
-	    !intel_wm_plane_visible(cstate, intel_pstate)) {
+	if (latency == 0) {
 		result->plane_en = false;
 		return 0;
 	}
@@ -4805,9 +4805,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	enum plane_id intel_plane_id = intel_plane->id;
 	int ret;
 
-	if (WARN_ON(!intel_pstate->base.fb))
-		return -EINVAL;
-
 	ddb_blocks = plane_id ?
 		     skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :
 		     skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);
@@ -4876,9 +4873,6 @@ static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
 	const uint16_t trans_amount = 10; /* This is configurable amount */
 	uint16_t wm0_sel_res_b, trans_offset_b, res_blocks;
 
-	if (!cstate->base.active)
-		goto exit;
-
 	/* Transition WM are not recommended by HW team for GEN9 */
 	if (INTEL_GEN(dev_priv) <= 9)
 		goto exit;
@@ -4965,6 +4959,9 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 		if (ret)
 			return ret;
 
+		if (!wm_params.plane_visible)
+			continue;
+
 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
 					    intel_pstate, &wm_params, wm, 0);
 		if (ret)
-- 
2.14.4