[Intel-gfx] [RFC 7/8] drm/i915: Sort platform if cases from newer-to-older.
Jani Nikula
jani.nikula at linux.intel.com
Fri Oct 19 08:07:58 UTC 2018
On Thu, 18 Oct 2018, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> Let's use this whenever it makes sense and code gets
> easier to read.
Ack on this general direction.
BR,
Jani.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 18 +++++++++---------
> drivers/gpu/drm/i915/intel_dp.c | 24 +++++++++++++-----------
> drivers/gpu/drm/i915/intel_pm.c | 6 +++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_uncore.c | 2 +-
> 5 files changed, 32 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 10b5314f266c..498521a3bc21 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1737,16 +1737,16 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (INTEL_GEN(dev_priv) <= 8)
> - hsw_ddi_clock_get(encoder, pipe_config);
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_GEN10(dev_priv))
> + cnl_ddi_clock_get(encoder, pipe_config);
> else if (IS_GEN9_BC(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> - else if (IS_GEN10(dev_priv))
> - cnl_ddi_clock_get(encoder, pipe_config);
> - else if (INTEL_GEN(dev_priv) >= 11)
> - icl_ddi_clock_get(encoder, pipe_config);
> + else if (INTEL_GEN(dev_priv) <= 8)
> + hsw_ddi_clock_get(encoder, pipe_config);
> }
>
> void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
> @@ -3373,10 +3373,10 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
> void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
> struct intel_crtc_state *crtc_state)
> {
> - if (IS_GEN10(dev_priv) && crtc_state->port_clock > 594000)
> - crtc_state->min_voltage_level = 2;
> - else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
> + if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
> crtc_state->min_voltage_level = 1;
> + else if (IS_GEN10(dev_priv) && crtc_state->port_clock > 594000)
> + crtc_state->min_voltage_level = 2;
> }
>
> void intel_ddi_get_config(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0ea0414ccef4..3c13a49b4a7a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5035,20 +5035,22 @@ bool intel_digital_port_connected(struct intel_encoder *encoder)
> return g4x_digital_port_connected(encoder);
> }
>
> - if (IS_GEN5(dev_priv))
> - return ilk_digital_port_connected(encoder);
> - else if (IS_GEN6(dev_priv))
> - return snb_digital_port_connected(encoder);
> - else if (IS_GEN7(dev_priv))
> - return ivb_digital_port_connected(encoder);
> - else if (IS_GEN8(dev_priv))
> - return bdw_digital_port_connected(encoder);
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_digital_port_connected(encoder);
> + else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv))
> + return spt_digital_port_connected(encoder);
> else if (IS_GEN9_LP(dev_priv))
> return bxt_digital_port_connected(encoder);
> - else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> - return spt_digital_port_connected(encoder);
> + else if (IS_GEN8(dev_priv))
> + return bdw_digital_port_connected(encoder);
> + else if (IS_GEN7(dev_priv))
> + return ivb_digital_port_connected(encoder);
> + else if (IS_GEN6(dev_priv))
> + return snb_digital_port_connected(encoder);
> + else if (IS_GEN5(dev_priv))
> + return ilk_digital_port_connected(encoder);
> else
> - return icl_digital_port_connected(encoder);
> + return false;
> }
>
> static struct edid *
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f4b7fd132173..5663b7059467 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3724,12 +3724,12 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
> if (!intel_has_sagv(dev_priv))
> return false;
>
> - if (IS_GEN9(dev_priv))
> - sagv_block_time_us = 30;
> + if (INTEL_GEN(dev_priv) >= 11)
> + sagv_block_time_us = 10;
> else if (IS_GEN10(dev_priv))
> sagv_block_time_us = 20;
> else
> - sagv_block_time_us = 10;
> + sagv_block_time_us = 30;
>
> /*
> * SKL+ workaround: bspec recommends we disable the SAGV when we have
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 1d7dd506708a..9472cd895ea6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3084,14 +3084,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> */
> if (INTEL_GEN(dev_priv) >= 11) {
> err = set_power_wells(power_domains, icl_power_wells);
> - } else if (IS_HASWELL(dev_priv)) {
> - err = set_power_wells(power_domains, hsw_power_wells);
> - } else if (IS_BROADWELL(dev_priv)) {
> - err = set_power_wells(power_domains, bdw_power_wells);
> - } else if (IS_GEN9_BC(dev_priv)) {
> - err = set_power_wells(power_domains, skl_power_wells);
> } else if (IS_GEN10(dev_priv)) {
> err = set_power_wells(power_domains, cnl_power_wells);
> + } else if (IS_GEN9_BC(dev_priv)) {
> + err = set_power_wells(power_domains, skl_power_wells);
>
> /*
> * DDI and Aux IO are getting enabled for all ports
> @@ -3106,8 +3102,12 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> err = set_power_wells(power_domains, bxt_power_wells);
> } else if (IS_GEMINILAKE(dev_priv)) {
> err = set_power_wells(power_domains, glk_power_wells);
> + } else if (IS_BROADWELL(dev_priv)) {
> + err = set_power_wells(power_domains, bdw_power_wells);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> err = set_power_wells(power_domains, chv_power_wells);
> + } else if (IS_HASWELL(dev_priv)) {
> + err = set_power_wells(power_domains, hsw_power_wells);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> err = set_power_wells(power_domains, vlv_power_wells);
> } else if (IS_I830(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 3ad302c66254..9289515108c3 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> FORCEWAKE_MEDIA_VEBOX_GEN11(i),
> FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
> }
> - } else if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
> + } else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) {
> dev_priv->uncore.funcs.force_wake_get =
> fw_domains_get_with_fallback;
> dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
--
Jani Nikula, Intel Open Source Graphics Center
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