[Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

[Rodrigo Vivi]

Let's add a platform has_sagv instead of having a full
function that handle platform by platform.

The specially case for SKL for not controlled sagv
is already taken care inside intel_enable_sagv, so there's
no need to duplicate the check here.

v2: Go one step further and remove skl special case. (Jani)

Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Lucas De Marchi <lucas.demarchi at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c          | 20 +++-----------------
 4 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef037fed..8eab6bdff8a4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2650,6 +2650,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
+#define HAS_SAGV(dev_priv)		 ((dev_priv)->info.has_sagv && \
+					  dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
 
 #define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
 #define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0a05cc7ace14..21ca9917b86e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -465,6 +465,7 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_csr = 1, \
 	.has_guc = 1, \
 	.has_ipc = 1, \
+	.has_sagv = 1, \
 	.ddb_size = 896
 
 #define SKL_PLATFORM \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index af7002640cdf..e77c8b62783f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -117,6 +117,7 @@ enum intel_ppgtt {
 	func(hws_needs_physical); \
 	func(overlay_needs_physical); \
 	func(supports_tv); \
+	func(has_sagv); \
 	func(has_ipc);
 
 #define GEN_MAX_SLICES		(6) /* CNL upper bound */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67a4d0735291..09c21f6151fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3609,20 +3609,6 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
 	return false;
 }
 
-static bool
-intel_has_sagv(struct drm_i915_private *dev_priv)
-{
-	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
-	    IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
-		return true;
-
-	if (IS_SKYLAKE(dev_priv) &&
-	    dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
-		return true;
-
-	return false;
-}
-
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3639,7 +3625,7 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
 
-	if (!intel_has_sagv(dev_priv))
+	if (!HAS_SAGV(dev_priv))
 		return 0;
 
 	if (dev_priv->sagv_status == I915_SAGV_ENABLED)
@@ -3676,7 +3662,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 {
 	int ret;
 
-	if (!intel_has_sagv(dev_priv))
+	if (!HAS_SAGV(dev_priv))
 		return 0;
 
 	if (dev_priv->sagv_status == I915_SAGV_DISABLED)
@@ -3721,7 +3707,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	int level, latency;
 	int sagv_block_time_us;
 
-	if (!intel_has_sagv(dev_priv))
+	if (!HAS_SAGV(dev_priv))
 		return false;
 
 	if (IS_GEN9(dev_priv))
-- 
2.19.1