[Intel-gfx] [PATCH v7 14/23] drm/i915/icl: Define DSI transcoder timing registers

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan at intel.com>
>
> This patch defines registers and bitfields used for
> programming DSI transcoder's horizontal and vertical
> timings.
>
> v2: Remove TRANS_TIMING_SHIFT definition
>
> v3 by Jani:
>   - Group macros by transcoder

Separation of DSI0 and DSI 1 specific registers are fine.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 79e633c1e9ad..c4270ca26a11 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4061,6 +4061,20 @@ enum {
>   #define _VSYNCSHIFT_B	0x61028
>   #define _PIPE_MULT_B	0x6102c
>   
> +/* DSI 0 timing regs */
> +#define _HTOTAL_DSI0		0x6b000
> +#define _HSYNC_DSI0		0x6b008
> +#define _VTOTAL_DSI0		0x6b00c
> +#define _VSYNC_DSI0		0x6b014
> +#define _VSYNCSHIFT_DSI0	0x6b028
> +
> +/* DSI 1 timing regs */
> +#define _HTOTAL_DSI1		0x6b800
> +#define _HSYNC_DSI1		0x6b808
> +#define _VTOTAL_DSI1		0x6b80c
> +#define _VSYNC_DSI1		0x6b814
> +#define _VSYNCSHIFT_DSI1	0x6b828
> +
>   #define TRANSCODER_A_OFFSET 0x60000
>   #define TRANSCODER_B_OFFSET 0x61000
>   #define TRANSCODER_C_OFFSET 0x62000