[Intel-gfx] [PATCH v7 16/23] drm/i915/icl: Define TRANS_CONF register for DSI

[Madhav Chauhan]

On 10/15/2018 7:58 PM, Jani Nikula wrote:
> From: Madhav Chauhan <madhav.chauhan at intel.com>
>
> This patch defines TRANS_CONF registers for DSI ports
> 0 and 1. Bitfields of these registers used for enabling
> and reading the current state of transcoder.
>
> v2: Add blank line before comment
>
> v3 by Jani:
>   - Move DSI specific .pipe_offsets to GEN11_FEATURES
>   - Macro placement and comment juggling

Changes looks ok.

Regards,
Madhav

>
> Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c | 3 +++
>   drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b86b735a8634..44e745921ac1 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
>   
>   #define GEN11_FEATURES \
>   	GEN10_FEATURES, \
> +	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
> +			  PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
> +			  PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
>   	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
>   			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
>   			   TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c4270ca26a11..839e681bd3a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5652,6 +5652,10 @@ enum {
>    */
>   #define PIPE_EDP_OFFSET	0x7f000
>   
> +/* ICL DSI 0 and 1 */
> +#define PIPE_DSI0_OFFSET	0x7b000
> +#define PIPE_DSI1_OFFSET	0x7b800
> +
>   #define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
>   	dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
>   	dev_priv->info.display_mmio_offset)
> @@ -6240,6 +6244,10 @@ enum {
>   #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
>   #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
>   
> +/* ICL DSI 0 and 1 */
> +#define _PIPEDSI0CONF		0x7b008
> +#define _PIPEDSI1CONF		0x7b808
> +
>   /* Sprite A control */
>   #define _DVSACNTR		0x72180
>   #define   DVS_ENABLE		(1 << 31)