[Intel-gfx] [PATCH 1/3] drm/i915: Make number of ddi ports explicit.

[Ville Syrjälä]

On Fri, Oct 19, 2018 at 01:19:43PM -0700, Rodrigo Vivi wrote:
> Instead of a simple bool that shows if we have ddi ports
> or not, let's highlight the number of ddi ports.
> 
> So we can use this information to determine the code
> path instead of using platforms codenames.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 2 +-
>  drivers/gpu/drm/i915/i915_pci.c          | 5 +++--
>  drivers/gpu/drm/i915/intel_device_info.h | 2 +-
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3017ef037fed..7ad232849268 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2647,7 +2647,7 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
>  
> -#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
> +#define HAS_DDI(dev_priv)		 ((dev_priv)->info.ddi_ports > 0)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 0a05cc7ace14..0427486f63d0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -363,7 +363,7 @@ static const struct intel_device_info intel_valleyview_info = {
>  #define G75_FEATURES  \
>  	GEN7_FEATURES, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> -	.has_ddi = 1, \
> +	.ddi_ports = 5, \
>  	.has_fpga_dbg = 1, \
>  	.has_psr = 1, \
>  	.has_dp_mst = 1, \
> @@ -505,7 +505,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
>  	.num_pipes = 3, \
>  	.has_64bit_reloc = 1, \
> -	.has_ddi = 1, \
> +	.ddi_ports = 3, \
>  	.has_fpga_dbg = 1, \
>  	.has_fbc = 1, \
>  	.has_psr = 1, \
> @@ -596,6 +596,7 @@ static const struct intel_device_info intel_cannonlake_info = {
>  #define GEN11_FEATURES \
>  	GEN10_FEATURES, \
>  	GEN(11), \
> +	.ddi_ports = 6, \
>  	.ddb_size = 2048, \
>  	.has_logical_ring_elsq = 1
>  
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index af7002640cdf..1be941222ed0 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -90,7 +90,6 @@ enum intel_ppgtt {
>  	/* Keep has_* in alphabetical order */ \
>  	func(has_64bit_reloc); \
>  	func(has_csr); \
> -	func(has_ddi); \
>  	func(has_dp_mst); \
>  	func(has_reset_engine); \
>  	func(has_fbc); \
> @@ -165,6 +164,7 @@ struct intel_device_info {
>  
>  	u32 display_mmio_offset;
>  
> +	u8 ddi_ports;

num_ddi_ports?

Or might we even want a bitmask?

>  	u8 num_pipes;
>  	u8 num_sprites[I915_MAX_PIPES];
>  	u8 num_scalers[I915_MAX_PIPES];
> -- 
> 2.19.1
> 
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-- 
Ville Syrjälä
Intel