[Intel-gfx] [PATCH v5 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants

[Srivatsa, Anusha]

________________________________________
From: Intel-gfx [intel-gfx-bounces at lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.navare at intel.com]
Sent: Friday, October 05, 2018 4:22 PM
To: intel-gfx at lists.freedesktop.org; dri-devel at lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants

DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec

v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2

Cc: dri-devel at lists.freedesktop.org
Cc: Jani Nikula <jani.nikula at linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>

---
 include/drm/drm_dsc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 0e5e3368d645..8562d8ee8161 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -41,6 +41,9 @@
 #define DSC_PPS_RC_RANGE_MINQP_SHIFT           11
 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT           6
 #define DSC_PPS_NATIVE_420_SHIFT               1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS         16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL          0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS         13

 /* Configuration for a single Rate Control model range */
 struct dsc_rc_range_parameters {
--
2.18.0

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