[Intel-gfx] [PATCH v1] ppgtt/i915: memory address masks
Sergii Romantsov
sergii.romantsov at gmail.com
Thu Oct 25 08:49:51 UTC 2018
Gen8+ ppgtt uses 48-bit addresses.
Kernel driver uses masks to manipulate with addresses.
Masks are UL-types. On 64-bit system UL is 64 bits,
on 32-bit system - 32.
So on 32-bit systems 48-bit adresses goes to be cut to 32 bits.
CC: Kenneth Graunke <kenneth at whitecape.org>
CC: Chris Wilson <chris at chris-wilson.co.uk>
CC: Lionel G Landwerlin <lionel.g.landwerlin at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Signed-off-by: Sergii Romantsov <sergii.romantsov at globallogic.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f00c7fbe..fa3c6e4 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2358,7 +2358,7 @@ static void gen6_check_and_clear_faults(struct drm_i915_private *dev_priv)
fault = I915_READ(RING_FAULT_REG(engine));
if (fault & RING_FAULT_VALID) {
DRM_DEBUG_DRIVER("Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
+ "\tAddr: 0x%08llx\n"
"\tAddress space: %s\n"
"\tSource ID: %d\n"
"\tType: %d\n",
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 2a116a9..02087ca 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -676,6 +676,11 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#define PIN_HIGH BIT(9)
#define PIN_OFFSET_BIAS BIT(10)
#define PIN_OFFSET_FIXED BIT(11)
-#define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
+#define PIN_OFFSET_MASK (-(__u64)I915_GTT_PAGE_SIZE)
+#undef PAGE_MASK /* NOTE(sergii.romantsov): seems not the best
+ * idea, but original PAGE_MASK can\t be used
+ * for ppgtt at least with 32-bit kernel.
+ */
+#define PAGE_MASK (~((__u64)PAGE_SIZE-1))
#endif
--
2.7.4
More information about the Intel-gfx
mailing list