[Intel-gfx] [FW: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT]

[Yuan, Hang]

Hi Chris,

I checked GVT shadow PPGTT handling codes and think GVT does propagate guest PTE flags to shadow PPGTT entry. Then I run i915 self-test case "igt_ctx_readonly" in KVMGT's guest. The case doesn't report any errors. Can I know if there are any other reasons that you think GVT breaks read-only support?

Thanks,
Henry

> ----- Forwarded message from Chris Wilson <chris at chris-wilson.co.uk> -----
> 
> Date: Thu, 12 Jul 2018 19:53:12 +0100
> From: Chris Wilson <chris at chris-wilson.co.uk>
> To: intel-gfx at lists.freedesktop.org
> Cc: Chris Wilson <chris at chris-wilson.co.uk>, Zhenyu Wang
> <zhenyuw at linux.intel.com>, Jon Bloomfield <jon.bloomfield at intel.com>,
> Joonas Lahtinen
> 	<joonas.lahtinen at linux.intel.com>, Matthew Auld
> <matthew.william.auld at gmail.com>
> Subject: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT
> X-Mailer: git-send-email 2.18.0
> 
> GVT is not propagating the PTE bits, and is always setting the read-write bit,
> thus breaking read-only support.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> Cc: Jon Bloomfield <jon.bloomfield at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Matthew Auld <matthew.william.auld at gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 6c0b438afe46..8e70a45b8a90 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1662,8 +1662,12 @@ static struct i915_hw_ppgtt
> *gen8_ppgtt_create(struct drm_i915_private *i915)
>  		1ULL << 48 :
>  		1ULL << 32;
> 
> -	/* From bdw, there is support for read-only pages in the PPGTT */
> -	ppgtt->vm.has_read_only = true;
> +	/*
> +	 * From bdw, there is support for read-only pages in the PPGTT.
> +	 *
> +	 * XXX GVT is not setting honouring the PTE bits.
> +	 */
> +	ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
> 
>  	i915_address_space_init(&ppgtt->vm, i915);
> 
> --
> 2.18.0
> 
> 
> ----- End forwarded message -----
> 
> --
> Open Source Technology Center, Intel ltd.
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