[Intel-gfx] [PATCH v2 3/4] drm/dp_mst: Check payload count in drm_dp_mst_atomic_check()

Daniel Vetter daniel at ffwll.ch
Mon Oct 29 14:25:37 UTC 2018


On Fri, Oct 26, 2018 at 04:35:48PM -0400, Lyude Paul wrote:
> It occurred to me that we never actually check this! So let's start
> doing that.
> 
> Signed-off-by: Lyude Paul <lyude at redhat.com>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

One thought on testing all this: I think long term some unti tests, where
we have a fake driver doing fake mst branch/ports and a bunch of
allocations and then checking that it all works and validates would be
nice. Longer term project ofc, and maybe after Kunit has been merged ...
-Daniel

> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
> index dcfab7536914..8bb03700e199 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3238,7 +3238,7 @@ int drm_dp_mst_atomic_check(struct drm_dp_mst_topology_state *state)
>  {
>  	struct drm_dp_mst_topology_mgr *mgr = state->mgr;
>  	struct drm_dp_vcpi_allocation *pos;
> -	int avail_slots = 63;
> +	int avail_slots = 63, payload_count = 0;
>  
>  	list_for_each_entry(pos, &state->vcpis, next) {
>  		DRM_DEBUG_ATOMIC("[MST PORT:%p] requires %d vcpi slots\n",
> @@ -3251,6 +3251,12 @@ int drm_dp_mst_atomic_check(struct drm_dp_mst_topology_state *state)
>  					 avail_slots + pos->vcpi);
>  			return -ENOSPC;
>  		}
> +
> +		if (++payload_count > mgr->max_payloads) {
> +			DRM_DEBUG_ATOMIC("[MST MGR:%p] state %p has too many payloads (max=%d)\n",
> +					 mgr, state, mgr->max_payloads);
> +			return -EINVAL;
> +		}
>  	}
>  	DRM_DEBUG_ATOMIC("[MST MGR:%p] state %p vcpi avail=%d used=%d\n",
>  			 mgr, state, avail_slots, 63 - avail_slots);
> -- 
> 2.17.2
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch


More information about the Intel-gfx mailing list