[Intel-gfx] [PATCH] drm/i915/gtt: Revert "Disable read-only support under GVT"

[Chris Wilson]

Quoting hang.yuan at linux.intel.com (2018-10-30 07:08:01)
> From: Hang Yuan <hang.yuan at linux.intel.com>
> 
> This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.
> 
> Checked GVT codes that guest PPGTT PTE flag bits are propagated
> to shadow PTE. Read/write bit is not changed. Further tested by
> i915 self-test case "igt_ctx_readonly". No error or GPU hang was
> detected. So enable read-only support under GVT.
> 
> Signed-off-by: Hang Yuan <hang.yuan at linux.intel.com>

Zhenyu, happy to give an r-b?
-Chris

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++------
>  1 file changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 19b2d99..bdf9f9f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1602,12 +1602,8 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
>                 1ULL << 48 :
>                 1ULL << 32;
>  
> -       /*
> -        * From bdw, there is support for read-only pages in the PPGTT.
> -        *
> -        * XXX GVT is not honouring the lack of RW in the PTE bits.
> -        */
> -       ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
> +       /* From bdw, there is support for read-only pages in the PPGTT. */
> +       ppgtt->vm.has_read_only = true;
>  
>         i915_address_space_init(&ppgtt->vm, i915);
>  
> -- 
> 2.7.4
> 
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