[Intel-gfx] [v4 4/7] i915/dp/fec: Add fec_enable to the crtc state.

[Anusha Srivatsa]

Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.

v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)

- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)

Suggested-by: Ville Syrjala <ville.syrjala at linux.intel.com>
Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
Cc: Jani Nikula <jani.nikula at linux.intel.com>
Cc: Manasi Navare <manasi.d.navare at intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c  | 25 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_drv.h |  3 +++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a344be555dd6..5ae3855925f3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2045,6 +2045,21 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 	return false;
 }
 
+static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	enum port port = dig_port->base.port;
+
+	return INTEL_GEN(dev_priv) >= 11 && port != PORT_A;
+}
+
+static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+				  struct intel_crtc_state *pipe_config)
+{
+	return intel_dp_source_supports_fec(intel_dp) &&
+		drm_dp_sink_supports_fec(intel_dp->fec_capable);
+}
 static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 					struct intel_crtc_state *pipe_config,
 					struct link_config_limits *limits)
@@ -2056,6 +2071,8 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	u16 dsc_max_output_bpp = 0;
 	u8 dsc_dp_slice_count = 0;
 
+	pipe_config->fec_enable = !intel_dp_is_edp(intel_dp);
+
 	if (INTEL_GEN(dev_priv) < 10 ||
 	    !drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))
 		return false;
@@ -2122,7 +2139,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 			  pipe_config->dsc_params.compressed_bpp);
 		return false;
 	}
-	pipe_config->dsc_params.compression_enable = true;
+
+	if (pipe_config->fec_enable && !intel_dp_supports_fec(intel_dp, pipe_config)) {
+		DRM_DEBUG_KMS("No FEC Support, disabling Compression");
+		pipe_config->dsc_params.compression_enable = false;
+	} else {
+		pipe_config->dsc_params.compression_enable = true;
+	}
 	DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
 		      "Compressed Bpp = %d Slice Count = %d\n",
 		      pipe_config->pipe_bpp,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9a94c6544bf5..9f701463219b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -940,6 +940,9 @@ struct intel_crtc_state {
 		u8 slice_count;
 	} dsc_params;
 	struct drm_dsc_config dp_dsc_cfg;
+
+	/* Forward Error correction State */
+	bool fec_enable;
 };
 
 struct intel_crtc {
-- 
2.17.1