[Intel-gfx] [PATCH] drm/i915: add LG eDP panel to quirk database
Dhinakaran Pandiyan
dhinakaran.pandiyan at intel.com
Fri Sep 7 00:08:23 UTC 2018
On Thu, 2018-09-06 at 14:19 +0000, Lee, Shawn C wrote:
> On Thu, 06 Sep 2018, Jani Nikula wrote:
> > > The N value was computed by kernel driver that based on
> > > synchronous
> > > clock mode. But only specific N value (0x8000) would be
> > > acceptable for
> > > LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock
> > > mode.
> >
> > As I wrote before, it's the DP source that determines between
> > synchronous and asynchronous clock mode, not the sink. The sink in
> > question appears to expect a
> > constant N related to asynchronous clock mode even when we're using
> > and advertising synchronous clock mode in DP Main Stream
> > Attributes.
> >
> > (It's possible a certain other OS uses the same constant N
> > regardless of clock mode, leading to the panel working by
> > coincidence.)
> >
>
> Yes, this sink device should not expect source will give specific N
> value. I have no idea what the other OS to calculate M/V value but
> vendor said they don't have similar issue before.
>
> > > With the other N value, Tcon will enter BITS mode and display
> > > black screen.
> > > Add this panel into quirk database and give particular N value
> > > when
> > > calculate M/N divider.
> > >
> > > Cc: Jani Nikula <jani.nikula at intel.com>
> >
> > Cc: Cooper Chiou <cooper.chiou at intel.com>
> > > Cc: Matt Atwood <matthew.s.atwood at intel.com>
> > > Signed-off-by: Lee, Shawn C <shawn.c.lee at intel.com>
> > > ---
> > > drivers/gpu/drm/drm_dp_helper.c | 10 +++++++++-
> > > drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++------
> > > drivers/gpu/drm/i915/intel_display.h | 3 ++-
> > > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > include/drm/drm_dp_helper.h | 1 +
> > > 6 files changed, 29 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > > b/drivers/gpu/drm/drm_dp_helper.c index
> > > 0cccbcb2d03e..a0259bbbe9df
> > > 100644
> > > --- a/drivers/gpu/drm/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > > @@ -1258,13 +1258,18 @@ struct dpcd_quirk {
> > > u8 oui[3];
> > > bool is_branch;
> > > u32 quirks;
> > > + u8 dev_id[6];
> >
> > Your commit message says nothing about the need to extend the quirk
> > mechanism to use the device ID. Do we really need it?
> >
> > If we do need it, please name it device_id like it is in struct
> > drm_dp_dpcd_ident, and place it after oui.
> >
>
> If we just recognize OUI. And didn't use device_id to identify which
> sink/branch device need specific M/N value.
> That means all the sink/branch device with Analogix OUI will apply
> this work around.
>
> 00-22-B9 (hex) Analogix Seminconductor, Inc
>
> > > };
> > >
> > > #define OUI(first, second, third) { (first), (second), (third) }
> > > +#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
> > > + { (first), (second), (third), (fourth), (fifth), (sixth)
> > > }
> > >
> > > static const struct dpcd_quirk dpcd_quirk_list[] = {
> > > /* Analogix 7737 needs reduced M and N at HBR2 link
> > > rates */
> > > - { OUI(0x00, 0x22, 0xb9), true,
> > > BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
> > > + { OUI(0x00, 0x22, 0xb9), true,
> > > BIT(DP_DPCD_QUIRK_LIMITED_M_N),
> > > +DEVICE_ID(0, 0, 0, 0, 0, 0) },
> >
> > Maybe add #define DEVICE_ID_ANY to initialize all to zero.
> >
> > > + /* LG LP140WF6-SPM1 eDP panel */
> > > + { OUI(0x00, 0x22, 0xb9), false,
> > > BIT(DP_DPCD_QUIRK_CONSTANT_N),
> > > +DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T') },
> > > };
> > >
> > > #undef OUI
> >
> > #undef DEVICE_ID
> > #undef DEVICE_ID_ANY
> >
> > > @@ -1293,6 +1298,9 @@ drm_dp_get_quirks(const struct
> > > drm_dp_dpcd_ident *ident, bool is_branch)
> > > if (memcmp(quirk->oui, ident->oui, sizeof(ident-
> > > >oui)) != 0)
> > > continue;
> > >
> > > + if (!is_branch && memcmp(quirk->dev_id, ident-
> > > >device_id, 6) != 0)
> > > + continue;
> > > +
> >
> > Why not branch devices? This is really a trick to avoid matching on
> > the Analogix device which you set to zeros, and now you require
> > device id match for all non-branch quirks. Not good. Please check
> > if the >quirk table has all zeros, and compare if not.
> >
>
> It will not compare device_id for branch device because of I don't
> have the device_id for Analogix 7737 branch device you debug before.
> So I set it to zero for default setup.
Cc'ing: Clint
>
> > > quirks |= quirk->quirks;
> > > }
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index ec3e24f07486..ff01a742b054 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6465,7 +6465,7 @@ static int
> > > ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
> > > pipe_config->fdi_lanes = lane;
> > >
> > > intel_link_compute_m_n(pipe_config->pipe_bpp, lane,
> > > fdi_dotclock,
> > > - link_bw, &pipe_config->fdi_m_n,
> > > false);
> > > + link_bw, &pipe_config->fdi_m_n,
> > > false, false);
> >
> > This is getting pretty ugly, to be honest. Which is why I was
> > wondering if we could actually turn the Analogix quirk into a
> > constant N...
> >
>
> Seems Anaglogix 7737 can't handle full 24-bit main link Mdiv and Ndiv
> main link attributes properly.
> Using constant N (0x8000) value should be acceptable. It would not
> exceed the Analogix 7737 limitation.
>
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe,
> > > pipe_config);
> > > if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { @@
> > > -6680,7
> > > +6680,7 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
> > >
> > > static void compute_m_n(unsigned int m, unsigned int n,
> > > uint32_t *ret_m, uint32_t *ret_n,
> > > - bool reduce_m_n)
> > > + bool reduce_m_n, bool constant_n)
> > > {
> > > /*
> > > * Reduce M/N as much as possible without loss in
> > > precision. Several
> > > DP @@ -6695,7 +6695,11 @@ static void compute_m_n(unsigned int m,
> > > unsigned int n,
> > > }
> > > }
> > >
> > > - *ret_n = min_t(unsigned int, roundup_pow_of_two(n),
> > > DATA_LINK_N_MAX);
> > > + if (constant_n)
> > > + *ret_n = 0x8000;
> > > + else
> > > + *ret_n = min_t(unsigned int,
> > > roundup_pow_of_two(n),
> > > +DATA_LINK_N_MAX);
> > > +
> > > *ret_m = div_u64((uint64_t) m * *ret_n, n);
> > > intel_reduce_m_n_ratio(ret_m, ret_n); } @@ -6704,18
> > > +6708,18 @@
> > > void intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > - bool reduce_m_n)
> > > + bool reduce_m_n, bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > compute_m_n(bits_per_pixel * pixel_clock,
> > > link_clock * nlanes * 8,
> > > &m_n->gmch_m, &m_n->gmch_n,
> > > - reduce_m_n);
> > > + reduce_m_n, constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > &m_n->link_m, &m_n->link_n,
> > > - reduce_m_n);
> > > + reduce_m_n, constant_n);
> > > }
> > >
> > > static inline bool intel_panel_use_ssc(struct drm_i915_private
> > > *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 43f080c6538d..dde7d73bd36d 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -379,7 +379,8 @@ struct intel_link_m_n { void
> > > intel_link_compute_m_n(int bpp, int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > - bool reduce_m_n);
> > > + bool reduce_m_n,
> > > + bool constant_n);
> > >
> > > bool is_ccs_modifier(u64 modifier);
> > > #endif
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c index
> > > 436c22de33b6..95edbac24919
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2000,6 +2000,8 @@ intel_dp_compute_config(struct
> > > intel_encoder *encoder,
> > > to_intel_digital_connector_state(conn_state);
> > > bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
> > > DP_DPCD_QUIRK_LIMITED
> > > _M_N);
> > > + bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
> > > + DP_DPCD_QUIRK_CONSTAN
> > > T_N);
> > >
> > > if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) &&
> > > port != PORT_A)
> > > pipe_config->has_pch_encoder = true; @@ -2064,7
> > > +2066,8 @@
> > > intel_dp_compute_config(struct intel_encoder *encoder,
> > > adjusted_mode->crtc_clock,
> > > pipe_config->port_clock,
> > > &pipe_config->dp_m_n,
> > > - reduce_m_n);
> > > + reduce_m_n,
> > > + constant_n);
> > >
> > > if (intel_connector->panel.downclock_mode != NULL &&
> > > dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
> > > @@ -2074,7 +2077,8
> > > @@ intel_dp_compute_config(struct intel_encoder *encoder,
> > > intel_connector-
> > > >panel.downclock_mode->clock,
> > > pipe_config-
> > > >port_clock,
> > > &pipe_config-
> > > >dp_m2_n2,
> > > - reduce_m_n);
> > > + reduce_m_n,
> > > + constant_n);
> > > }
> > >
> > > if (!HAS_DDI(dev_priv))
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > index 352e5216cc65..ac23982fa335 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > @@ -87,7 +87,7 @@ static bool intel_dp_mst_compute_config(struct
> > > intel_encoder *encoder,
> > > adjusted_mode->crtc_clock,
> > > pipe_config->port_clock,
> > > &pipe_config->dp_m_n,
> > > - reduce_m_n);
> > > + reduce_m_n, false);
> > >
> > > pipe_config->dp_m_n.tu = slots;
> > >
> > > diff --git a/include/drm/drm_dp_helper.h
> > > b/include/drm/drm_dp_helper.h
> > > index 05cc31b5db16..b1b2fd609c1c 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -1266,6 +1266,7 @@ enum drm_dp_quirk {
> > > * to 16 bits.
> > > */
> > > DP_DPCD_QUIRK_LIMITED_M_N,
> > > + DP_DPCD_QUIRK_CONSTANT_N,
> >
> > Documentation missing. See the comment for limited M/N.
> >
>
> I think we can remain DP_DPCD_QUIRK_LIMITED_M_N only and give these 2
> device the same N value.
>
> > BR,
> > Jani.
> >
> > > };
> > >
> > > /**
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
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