[Intel-gfx] [PATCH] drm/i915/chv: Update csc coefficient matrix during modeset

[Ville Syrjälä]

On Mon, Sep 10, 2018 at 06:31:22PM +0530, raviraj.p.sitaram at intel.com wrote:
> From: P Raviraj Sitaram <raviraj.p.sitaram at intel.com>
> 
> During modeset, previously configured csc coefficient matrix,if any, will
> not persist. This can result in blank screen as csc mode will be programmed
> while loading LUT but csc coefficient matrix remains unprogrammed.
> 
> Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b2bab57cd113..5029c0daa994 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6014,6 +6014,9 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	i9xx_set_pipeconf(intel_crtc);
>  
> +	if (IS_CHERRYVIEW(dev_priv))
> +		intel_color_set_csc(&pipe_config->base);
> +

No need for the platform check.

>  	intel_crtc->active = true;
>  
>  	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel