[Intel-gfx] [PATCH v2 02/23] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init

[Singh, Gaurav K]

On 8/1/2018 2:36 AM, Manasi Navare wrote:
> DSC is supported on eDP starting GEN 10 display and on DP starting
> GEN 11.
> This patch implements the discovery phase of DSC. On hotplug,
> source reads the DSC DPCD register set (0x00060 - 0x006F) to

Please correct it to 0x0006F in order to match the spec

> read the decompression capabilities of the sink device.
> This entire block of registers is cached in intel_dp so that
> capability information can be used during DSC configuration
> phase during compute_config phase of the modeset.
> For eDP, this caching happens during the eDP initialization.
> This caching is done only for eDP and DP rev >= 1.4
>
> v5:
> * Fix the block comment (Gaurav)
> * Use DRM_ERROR for dpcd_read fail (Gaurav,Anusha)
> v4:
> * Cache these only for Gen >= 11
> v3:
> * Remove the dsc_sink_support field in intel_dp (Jani N)
> v2:
> * Clear the cached registers on hotplug always (Jani N)
> * Combine the eDP and DP caching in same function (Jani N)
>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh at intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>

Except the above comment, this patch looks good to me..

Reviewed-by: Gaurav K Singh<gaurav.k.singh at intel.com>

> ---
>   drivers/gpu/drm/i915/intel_dp.c  | 32 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_drv.h |  1 +
>   2 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8e0e14b..afa4e2d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3877,6 +3877,29 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>   	return intel_dp->dpcd[DP_DPCD_REV] != 0;
>   }
>   
> +static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
> +{
> +	/*
> +	 *Clear the cached register set to avoid using stale values
> +	 * for the sinks that do not support DSC.
> +	 */
> +	memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
> +
> +	/* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
> +	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
> +	    intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
> +				     intel_dp->dsc_dpcd,
> +				     sizeof(intel_dp->dsc_dpcd)) < 0)
> +			DRM_ERROR("Failed to read DPCD register 0x%x\n",
> +				  DP_DSC_SUPPORT);
> +
> +		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
> +			      (int)sizeof(intel_dp->dsc_dpcd),
> +			      intel_dp->dsc_dpcd);
> +	}
> +}
> +
>   static bool
>   intel_edp_init_dpcd(struct intel_dp *intel_dp)
>   {
> @@ -3953,6 +3976,10 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>   
>   	intel_dp_set_common_rates(intel_dp);
>   
> +	/* Read the eDP DSC DPCD registers */
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> +		intel_dp_get_dsc_sink_cap(intel_dp);
> +
>   	return true;
>   }
>   
> @@ -4944,6 +4971,7 @@ intel_dp_long_pulse(struct intel_connector *connector)
>   
>   	if (status == connector_status_disconnected) {
>   		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
> +		memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>   
>   		if (intel_dp->is_mst) {
>   			DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
> @@ -4969,6 +4997,10 @@ intel_dp_long_pulse(struct intel_connector *connector)
>   
>   	intel_dp_print_rates(intel_dp);
>   
> +	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
> +	if (INTEL_GEN(dev_priv) >= 11)
> +		intel_dp_get_dsc_sink_cap(intel_dp);
> +
>   	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
>   			 drm_dp_is_branch(intel_dp->dpcd));
>   
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 99a5f5b..29abe7a 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1070,6 +1070,7 @@ struct intel_dp {
>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>   	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> +	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
>   	/* source rates */
>   	int num_source_rates;
>   	const int *source_rates;