[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs

Patchwork patchwork at emeril.freedesktop.org
Tue Sep 11 13:50:00 UTC 2018


== Series Details ==

Series: series starting with [01/26] drm/i915/ringbuffer: Reload PDs harder on byt/bcs
URL   : https://patchwork.freedesktop.org/series/49476/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9de40986b147 drm/i915/ringbuffer: Reload PDs harder on byt/bcs
b9e2092df49e drm/i915: Reorder execobject[] to insert non-48b objects into the low 4G
f46fe87029ff drm/i915: Limit number of capture objects
15afc0fb5e45 drm/i915: Handle incomplete Z_FINISH for compressed error states
9a31f12210ea drm/i915: Clear the error PTE just once on finish
23e66541c511 drm/i915: Cache the error string
0871ba469085 drm/i915/overlay: Allocate physical registers from stolen
-:16: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 6a2c4232ece1 ("drm/i915: Make the physical object coherent with GTT")'
#16: 
	commit 6a2c4232ece145d8b5a8f95f767bd6d0d2d2f2bb

total: 1 errors, 0 warnings, 0 checks, 358 lines checked
c32da9127a1f drm/i915/overlay: Use the ioctl parameters directly
08f507254f93 drm/i915/execlists: Reset CSB pointers on canceling requests (wedging)
290e940a72d3 drm/i915/execlists: Avoid kicking priority on the current context
c2feee8968a4 drm/i915/selftests: Basic stress test for rapid context switching
7505baf59285 drm/i915/execlists: Delay updating ring register state after resume
28400c1b7b09 drm/i915/execlists: Use coherent writes into the context image
aac3ebe81400 drm/i915/execlists: Onion unwind for logical_ring_init() failure
cb23ad1b2375 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#9: 
<0>[  531.960431] drv_self-4806    7.... 527402570us : intel_gpu_reset: engine_mask=1, ret=0, retry=0

total: 0 errors, 1 warnings, 0 checks, 7 lines checked
20da3956671d drm/i915: Report the number of closed vma held by each context in debugfs
-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/i915/i915_debugfs.c:350:
+		seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \

total: 0 errors, 1 warnings, 0 checks, 169 lines checked
28012de36835 drm/i915: Remove debugfs/i915_ppgtt_info
d49d4fa7f977 drm/i915: Track all held rpm wakerefs
-:105: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#105: FILE: drivers/gpu/drm/i915/i915_drv.h:1294:
+	spinlock_t debug_lock;

total: 0 errors, 0 warnings, 1 checks, 571 lines checked
4e54576eb08a drm/i915: Markup paired operations on wakerefs
-:707: WARNING:NEW_TYPEDEFS: do not add new typedefs
#707: FILE: drivers/gpu/drm/i915/i915_drv.h:131:
+typedef depot_stack_handle_t intel_wakeref_t;

total: 0 errors, 1 warnings, 0 checks, 1970 lines checked
e99e0144c2a0 drm/i915: Syntatic sugar for using intel_runtime_pm
-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+	for (wf = intel_runtime_pm_get(i915); wf; \
+	     intel_runtime_pm_put(i915, wf), wf = 0)

-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+	for (wf = intel_runtime_pm_get(i915); wf; \
+	     intel_runtime_pm_put(i915, wf), wf = 0)

-:495: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#495: FILE: drivers/gpu/drm/i915/intel_drv.h:2066:
+#define with_intel_runtime_pm_if_in_use(i915, wf) \
+	for (wf = intel_runtime_pm_get_if_in_use(i915); wf; \
+	     intel_runtime_pm_put(i915, wf), wf = 0)

-:495: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#495: FILE: drivers/gpu/drm/i915/intel_drv.h:2066:
+#define with_intel_runtime_pm_if_in_use(i915, wf) \
+	for (wf = intel_runtime_pm_get_if_in_use(i915); wf; \
+	     intel_runtime_pm_put(i915, wf), wf = 0)

total: 0 errors, 0 warnings, 4 checks, 569 lines checked
0f6bcf238601 drm/i915: Markup paired operations on display power domains
dd7335ca2592 drm/i915: Track the wakeref used to initialise display power domains
-:207: WARNING:LINE_SPACING: Missing a blank line after declarations
#207: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:4112:
+	struct i915_power_domains *power_domains = &i915->power_domains;
+	intel_wakeref_t wakeref __maybe_unused =

-:224: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "i915->csr.dmc_payload"
#224: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:4126:
+	    i915->csr.dmc_payload != NULL) {

total: 0 errors, 1 warnings, 1 checks, 320 lines checked
aaceeead6988 drm/i915/dp: Markup pps lock power well
-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dp' - possible side-effects?
#52: FILE: drivers/gpu/drm/i915/intel_dp.c:682:
+#define with_pps_lock(dp, wf) \
+	for (wf = pps_lock(dp); wf; wf = pps_unlock(dp, wf))

-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#52: FILE: drivers/gpu/drm/i915/intel_dp.c:682:
+#define with_pps_lock(dp, wf) \
+	for (wf = pps_lock(dp); wf; wf = pps_unlock(dp, wf))

total: 0 errors, 0 warnings, 2 checks, 425 lines checked
88b1d112dd9d drm/i915: Complain if hsw_get_pipe_config acquires the same power well twice
dd26c97c9761 drm/i915: Mark up Ironlake ips with rpm wakerefs
-:210: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#210: FILE: drivers/gpu/drm/i915/intel_pm.c:7970:
+	chipset_val = graphics_val = 0;

total: 0 errors, 0 warnings, 1 checks, 318 lines checked
a8d5adacb456 drm/i915: Serialise concurrent calls to i915_gem_set_wedged()
-:48: WARNING:MEMORY_BARRIER: memory barrier without comment
#48: FILE: drivers/gpu/drm/i915/i915_gem.c:3403:
+	smp_mb__before_atomic();

total: 0 errors, 1 warnings, 0 checks, 107 lines checked



More information about the Intel-gfx mailing list