[Intel-gfx] [PATCH v5 05/13] drm/i915/icl: Program T_INIT_MASTER registers

[Jani Nikula]

On Tue, 10 Jul 2018, Madhav Chauhan <madhav.chauhan at intel.com> wrote:
> This patch programs the time (in escape clocks) to drive
> the link in the initialization (i.e. LP-11) state.
>
> v2: Rebase
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> ---
>  drivers/gpu/drm/i915/icl_dsi.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index 41faa19..bc27e34 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -270,6 +270,22 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u32 tmp;
> +	enum port port;
> +
> +	/* Program T-INIT master registers */
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port));
> +		tmp &= ~MASTER_INIT_TIMER_MASK;
> +		tmp |= intel_dsi->init_count;
> +		I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp);
> +	}

Mmh, the high word is MBZ so the RMW is unnecessary. But *shrug*.

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


> +}
> +
>  static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  {
>  	/* step 4a: power up all lanes of the DDI used by DSI */
> @@ -283,6 +299,9 @@ static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
>  
>  	/* step 4d: enable DDI buffer */
>  	gen11_dsi_enable_ddi_buffer(encoder);
> +
> +	/* step 4e: setup D-PHY timings */
> +	gen11_dsi_setup_dphy_timings(encoder);
>  }
>  
>  static void __attribute__((unused))

-- 
Jani Nikula, Intel Open Source Graphics Center