[Intel-gfx] [RFC 0/3] Enable ICL DSI PLL

[Vandita Kulkarni]

Gen11/ICL DSI has to choose one of the free available DPLL which can also be
tied to DDI A/B combo phy ports. In legacy platforms that was not the case as
DSI had separate/exclusive PLLs.

ICL DPLL enable/disable steps are 80% common if DPLL is tied to DDI interface
(HDMI/DP) or DSI. If DSI implements separate PLL enable/disable
sequence like in legacy platform, lot of duplicate code will be added
which is not the right way.

Current DPLL enable/disable functions has some steps specific to DP/HDMI
and require some redesign if DSI has to use these existing DPLL functions.

RFC in this series alter existing DPLL functions to have common code for
enabling DPLL and move encoder specific code (DP/HDMI/DSI) to encoder
files.

Currently changes are for *enabling DPLL only*. If this approach looks
fine, RFC for disabling PLL will also be added. These RFC patches has
been tested and Single/Dual Link Video mode works fine tested with
https://github.com/madhavchauhan/Intel-DSI-Driver.git

These RFC patches are developed on top of following published series:
https://patchwork.freedesktop.org/series/44823/

Madhav Chauhan (3):
  drm/i915/icl: Restructure ICL DPLL enable functionality
  drm/i915/icl: Enable Gen11 DSI PLL
  drm/i915/icl: Calculate DPLL params for DSI

 drivers/gpu/drm/i915/icl_dsi.c        | 41 ++++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c      | 12 ++++++++++
 drivers/gpu/drm/i915/intel_display.c  |  4 +++-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 26 +++++++---------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 +-
 5 files changed, 64 insertions(+), 21 deletions(-)

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1.9.1