[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Per context dynamic (sub)slice power-gating (rev3)

[Patchwork]

== Series Details ==

Series: Per context dynamic (sub)slice power-gating (rev3)
URL   : https://patchwork.freedesktop.org/series/48194/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1c5fbd789ec4 drm/i915/execlists: Move RPCS setup to context pin
7bdb7605a619 drm/i915: Record the sseu configuration per-context & engine
cb0997071642 drm/i915/perf: lock powergating configuration to default when active
5dd5511a2f86 drm/i915: Add timeline barrier support
769a1cfec93c drm/i915: Expose RPCS (SSEU) configuration to userspace
-:40: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#40: 
v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel)

total: 0 errors, 1 warnings, 0 checks, 451 lines checked
c660f495e4ae drm/i915/icl: Support co-existance between per-context SSEU and OA
-:4: WARNING:TYPO_SPELLING: 'existance' may be misspelled - perhaps 'existence'?
#4: 
Subject: [PATCH] drm/i915/icl: Support co-existance between per-context SSEU

total: 0 errors, 1 warnings, 0 checks, 33 lines checked