[Intel-gfx] [PATCH 04/40] drm/i915: Park the GPU on module load

Chris Wilson chris at chris-wilson.co.uk
Thu Sep 20 14:52:27 UTC 2018


Quoting Tvrtko Ursulin (2018-09-20 15:02:36)
> 
> On 19/09/2018 20:55, Chris Wilson wrote:
> > Once we have flushed the first request through the system to both load a
> > context and record the default state; tell the GPU to park and idle
> > itself, putting itself immediately (hopefully at least) into a
> > powersaving state, and allowing ourselves to start from known state
> > after setting up all our bookkeeping.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index a94d5a308c4d..6b347ffb996b 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -5417,6 +5417,14 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915)
> >   
> >       assert_kernel_context_is_current(i915);
> >   
> > +     /*
> > +      * Immediately park the GPU so that we enable powersaving and
> > +      * treat it as idle. The next time we issue a request, we will
> > +      * unpark and start using the engine->pinned_default_state, otherwise
> > +      * it is in limbo and an early reset may fail.
> > +      */
> > +     __i915_gem_park(i915);
> > +
> >       for_each_engine(engine, i915, id) {
> >               struct i915_vma *state;
> >               void *vaddr;
> > 
> 
> Presumably the previous patch will make this pass CI?

Aye. There was an earlier series of just this pair to check that I had
caught all the missing wakerefs uncovered by idling on init.
 
> I would prefer the parking is done from the caller level but we couldn't 
> agree on this minor detail so anyway:
 
I wanted to postpone that idea until we have the rc6 setup refactored,
as I think that may open some more interesting avenues of how to handle
this.
-Chris


More information about the Intel-gfx mailing list