[Intel-gfx] [RFC 2/4] drm/i915/registers: prefer BIT() for single bits

[Jani Nikula]

BIT() is the preferred way of defining bits in the kernel.

Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++++++--------
 drivers/gpu/drm/i915/intel_dp.c |  2 +-
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25efce1eded7..893628c86a8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4612,7 +4612,7 @@ enum {
 
 #define _PP_STATUS			0x61200
 #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
-#define   PP_ON				(1 << 31)
+#define   PP_ON				BIT(31)
 /*
  * Indicates that all dependencies of the panel are on:
  *
@@ -4620,13 +4620,13 @@ enum {
  * - pipe enabled
  * - LVDS/DVOB/DVOC on
  */
-#define   PP_READY			(1 << 30)
+#define   PP_READY			BIT(30)
 #define   PP_SEQUENCE_MASK		GENMASK(29, 28)
 #define   PP_SEQUENCE_NONE		(0 << 28)
 #define   PP_SEQUENCE_POWER_UP		(1 << 28)
 #define   PP_SEQUENCE_POWER_DOWN	(2 << 28)
 #define   PP_SEQUENCE_SHIFT		28
-#define   PP_CYCLE_DELAY_ACTIVE		(1 << 27)
+#define   PP_CYCLE_DELAY_ACTIVE		BIT(27)
 #define   PP_SEQUENCE_STATE_MASK	GENMASK(3, 0)
 #define   PP_SEQUENCE_STATE_OFF_IDLE	(0x0 << 0)
 #define   PP_SEQUENCE_STATE_OFF_S0_1	(0x1 << 0)
@@ -4644,11 +4644,10 @@ enum {
 #define  PANEL_UNLOCK_REGS		(0xabcd << 16)
 #define  BXT_POWER_CYCLE_DELAY_MASK	GENMASK(8, 4)
 #define  BXT_POWER_CYCLE_DELAY_SHIFT	4
-#define  EDP_FORCE_VDD			(1 << 3)
-#define  EDP_BLC_ENABLE			(1 << 2)
-#define  PANEL_POWER_RESET		(1 << 1)
-#define  PANEL_POWER_OFF		(0 << 0)
-#define  PANEL_POWER_ON			(1 << 0)
+#define  EDP_FORCE_VDD			BIT(3)
+#define  EDP_BLC_ENABLE			BIT(2)
+#define  PANEL_POWER_RESET		BIT(1)
+#define  PANEL_POWER_ON			BIT(0)
 
 #define _PP_ON_DELAYS			0x61208
 #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6b4c19123f2a..ed06876457b7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1040,7 +1040,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 		/* 0x1F write to PP_DIV_REG sets max cycle delay */
 		I915_WRITE(pp_div_reg, pp_div | 0x1F);
-		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
 		msleep(intel_dp->panel_power_cycle_delay);
 	}
 
-- 
2.11.0