[Intel-gfx] [PATCH] drm/i915: Make RING_PDP relative to engine->mmio_base
Tvrtko Ursulin
tvrtko.ursulin at linux.intel.com
Fri Apr 5 13:11:48 UTC 2019
On 05/04/2019 13:38, Chris Wilson wrote:
> The PDP registers are an oddity inside the set of context saved
> registers in that they take the engine as a parameter to the macro and
> not the mmio_base as the others do. Make it accept the engine->mmio_base
> for consistency in programming the context registers.
>
> add/remove: 0/0 grow/shrink: 2/1 up/down: 3/-32 (-29)
> Function old new delta
> emit_ppgtt_update 324 326 +2
> capture 5102 5103 +1
> execlists_init_reg_state.isra 1128 1096 -32
>
> And similar savings later!
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 9 +++++----
> drivers/gpu/drm/i915/i915_gpu_error.c | 15 +++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/intel_lrc.c | 21 +++++++++++----------
> 4 files changed, 27 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f8c94405670b..66b6852cb4d2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -1028,6 +1028,7 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
> {
> struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
> struct intel_engine_cs *engine = rq->engine;
> + u32 base = engine->mmio_base;
> u32 *cs;
> int i;
>
> @@ -1040,9 +1041,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
>
> *cs++ = MI_LOAD_REGISTER_IMM(2);
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, 0));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, 0));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, 0));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, 0));
> *cs++ = lower_32_bits(pd_daddr);
>
> *cs++ = MI_NOOP;
> @@ -1056,9 +1057,9 @@ static int emit_ppgtt_update(struct i915_request *rq, void *data)
> for (i = GEN8_3LVL_PDPES; i--; ) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
> *cs++ = lower_32_bits(pd_daddr);
> }
> *cs++ = MI_NOOP;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c65d45bc63ee..43b68fdc8967 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1215,20 +1215,23 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
>
> ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
>
> - if (IS_GEN(dev_priv, 6))
> + if (IS_GEN(dev_priv, 6)) {
> ee->vm_info.pp_dir_base =
> ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
> - else if (IS_GEN(dev_priv, 7))
> + } else if (IS_GEN(dev_priv, 7)) {
> ee->vm_info.pp_dir_base =
> - ENGINE_READ(engine, RING_PP_DIR_BASE);
> - else if (INTEL_GEN(dev_priv) >= 8)
> + ENGINE_READ(engine, RING_PP_DIR_BASE);
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> + u32 base = engine->mmio_base;
> +
> for (i = 0; i < 4; i++) {
> ee->vm_info.pdp[i] =
> - I915_READ(GEN8_RING_PDP_UDW(engine, i));
> + I915_READ(GEN8_RING_PDP_UDW(base, i));
> ee->vm_info.pdp[i] <<= 32;
> ee->vm_info.pdp[i] |=
> - I915_READ(GEN8_RING_PDP_LDW(engine, i));
> + I915_READ(GEN8_RING_PDP_LDW(base, i));
> }
> + }
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00e03560c4e7..c18caa76f27c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -439,8 +439,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
> #define PP_DIR_DCLV_2G 0xffffffff
>
> -#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
> -#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
> +#define GEN8_RING_PDP_UDW(base, n) _MMIO((base) + 0x270 + (n) * 8 + 4)
> +#define GEN8_RING_PDP_LDW(base, n) _MMIO((base) + 0x270 + (n) * 8)
>
> #define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
> #define GEN8_RPCS_ENABLE (1 << 31)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index b662a054f228..6931dbb2888c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1451,10 +1451,11 @@ static int emit_pdps(struct i915_request *rq)
> *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED;
> for (i = GEN8_3LVL_PDPES; i--; ) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
> + u32 base = engine->mmio_base;
>
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(base, i));
> *cs++ = upper_32_bits(pd_daddr);
> - *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
> + *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(base, i));
> *cs++ = lower_32_bits(pd_daddr);
> }
> *cs++ = MI_NOOP;
> @@ -2729,14 +2730,14 @@ static void execlists_init_reg_state(u32 *regs,
>
> CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
> /* PDP values well be assigned later if needed */
> - CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
> - CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
> - CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
> - CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
> - CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
> - CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
> - CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
> - CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
> + CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(base, 3), 0);
> + CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(base, 3), 0);
> + CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(base, 2), 0);
> + CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(base, 2), 0);
> + CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(base, 1), 0);
> + CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(base, 1), 0);
> + CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(base, 0), 0);
> + CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(base, 0), 0);
>
> if (i915_vm_is_4lvl(&ppgtt->vm)) {
> /* 64b PPGTT (48bit canonical)
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Regards,
Tvrtko
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