[Intel-gfx] [PATCH 2/2] drm/i915: Simplify some icl pll calculations
Chris Wilson
chris at chris-wilson.co.uk
Mon Apr 8 16:14:17 UTC 2019
Quoting Ville Syrjälä (2019-04-08 17:06:01)
> On Mon, Apr 08, 2019 at 04:49:13PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-04-08 16:27:02)
> > > - /*
> > > - * Adjust the original formula to delay the division by 2^22 in order to
> > > - * minimize possible rounding errors.
> > > - */
> > > - tmp = (u64)m1 * m2_int * ref_clock +
> > > - (((u64)m1 * m2_frac * ref_clock) >> 22);
> > > - tmp = div_u64(tmp, 5 * div1 * div2);
> > > -
> > > - return tmp;
> > > + return div_u64(mul_u32_u32(ref_clock * m1, m2),
> > > + (5 * div1 * div2) << 22);
> >
> > You say the denominator here is a u64, so do you not need to cast
> > (u64)(5 * d1 * d2) to ensure it doesn't overflow the shift?
>
> It should fit into u32. The maximum value should be
> <= (5*0xf*0x7)<<22 based on the number of bits available
> for div1/2.
No worries, I was thinking div_u64 == div_u64_u64 anyway.
-Chris
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