[Intel-gfx] [PATCH 1/7] drm/i915: Use dedicated rc6 enabling sequence for gen11
chris at chris-wilson.co.uk
Tue Apr 9 17:04:15 UTC 2019
Quoting Michal Wajdeczko (2019-04-09 17:57:58)
> On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
> <mika.kuoppala at linux.intel.com> wrote:
> > +
> > + /*
> > + * 2c: Program Coarse Power Gating Policies.
> > + *
> > + * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
> > + * use instead is a more conservative estimate for the maximum time
> > + * it takes us to service a CS interrupt and submit a new ELSP - that
> > + * is the time which the GPU is idle waiting for the CPU to select the
> > + * next request to execute. If the idle hysteresis is less than that
> > + * interrupt service latency, the hardware will automatically gate
> > + * the power well and we will then incur the wake up cost on top of
> > + * the service latency. A similar guide from intel_pstate is that we
> > + * do not want the enable hysteresis to less than the wakeup latency.
> > + *
> > + * igt/gem_exec_nop/sequential provides a rough estimate for the
> > + * service latency, and puts it around 10us for Broadwell (and other
> > + * big core) and around 40us for Broxton (and other low power cores).
> > + * [Note that for legacy ringbuffer submission, this is less than 1us!]
> > + * However, the wakeup latency on Broxton is closer to 100us. To be
> > + * conservative, we have to factor in a context switch on top (due
> > + * to ksoftirqd).
> > + */
> Do we want to copy legacy comments to Gen11 specific function ?
The comment isn't legacy until you crunch through the measurements to
work out the minimum tolerances that are sensible for us.
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