[Intel-gfx] [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats

[Dhinakaran Pandiyan]

On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> 6bpc is only legal for RGB and RAW pixel encodings. For the rest
> the minimum is 8bpc. Set our lower limit accordingly.

Patch doesn't apply anymore, got a conflict in intel_drv.h. 


> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c     | 10 +++++++++-
>  drivers/gpu/drm/i915/intel_dp_mst.c |  2 +-
>  drivers/gpu/drm/i915/intel_drv.h    |  1 +
>  3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2aee526ed632..149fdfbcb343 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2002,6 +2002,14 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  	return 0;
>  }
>  
> +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
> +		return 6 * 3;
> +	else
> +		return 8 * 3;
Code matches spec, however I think there is a possibility of min_bpp becoming
greater than max_bpp. The max_bpc property allows user space to set a value of 6
and limits.min_bpp can become 24 because of the code above. Add a check for that
in compute_link_config()? Probably would mess up the compute_config() loop too.


> +}
> +
>  static int
>  intel_dp_compute_link_config(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config,
> @@ -2025,7 +2033,7 @@ intel_dp_compute_link_config(struct intel_encoder
> *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = 6 * 3;
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config);
>  	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>  
>  	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 6d2af7cf48e6..79c229184873 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -119,7 +119,7 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>  	limits.min_lane_count =
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = 6 * 3;
> +	limits.min_bpp = intel_dp_min_bpp(pipe_config);
>  	limits.max_bpp = pipe_config->pipe_bpp;
>  
>  	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index e79954c6271c..13f1b0367287 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1919,6 +1919,7 @@ void intel_dp_adjust_compliance_config(struct intel_dp
> *intel_dp,
>  				       struct link_config_limits *limits);
>  bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state);
> +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
>  bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
>  			   i915_reg_t dp_reg, enum port port,
>  			   enum pipe *pipe);