[Intel-gfx] [PATCH 7/7] drm/i915: Use Engine1 instance for gen11 pm interrupts
mika.kuoppala at linux.intel.com
Wed Apr 10 08:20:25 UTC 2019
Chris Wilson <chris at chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2019-04-09 17:13:10)
>> With gen11 the interrupt registers are shared between 2 engines,
>> with Engine1 instance being upper word and Engine0 instance being
>> lower. Annoyingly gen11 selected the pm interrupts to be in the
>> Engine1 instance.
> Sounds weird, but I can't fault the solution. The choice would either to
> have been shift pm_rps_events andadd gen11_pm_imr/_ier, so this patch
> looks to be the smaller delta.
Small wart added is one extra posting read on disabling.
I didn't like the under the hood shifting but the much
smaller delta was too tempting.
Perhaps a comment to the register definitions
would be warranted at minimum.
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