[Intel-gfx] [PATCH 6/7] drm/i915: Use Engine1 instance for gen11 pm interrupts

Chris Wilson chris at chris-wilson.co.uk
Wed Apr 10 13:39:06 UTC 2019

Quoting Mika Kuoppala (2019-04-10 11:59:22)
> With gen11 the interrupt registers are shared between 2 engines,
> with Engine1 instance being upper word and Engine0 instance being
> lower. Annoyingly gen11 selected the pm interrupts to be in the
> Engine1 instance.
> Rectify the situation by shifting the access accordingly,
> based on gen.
> v2: comments, warn on overzealous rps_events
> Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=108059
> Testcase: igt/i915_pm_rps at min-max-config-loaded
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Acked-by: Chris Wilson <chris at chris-wilson.co.uk>

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