[Intel-gfx] [PATCH 2/2] drm/i915: Simplify some icl pll calculations

[Ville Syrjälä]

On Mon, Apr 08, 2019 at 06:05:06PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-04-08 17:06:01)
> > On Mon, Apr 08, 2019 at 04:49:13PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2019-04-08 16:27:02)
> > > > -       /*
> > > > -        * Adjust the original formula to delay the division by 2^22 in order to
> > > > -        * minimize possible rounding errors.
> > > > -        */
> > > > -       tmp = (u64)m1 * m2_int * ref_clock +
> > > > -             (((u64)m1 * m2_frac * ref_clock) >> 22);
> > > > -       tmp = div_u64(tmp, 5 * div1 * div2);
> > > > -
> > > > -       return tmp;
> > > > +       return div_u64(mul_u32_u32(ref_clock * m1, m2),
> > > > +                      (5 * div1 * div2) << 22);
> > > 
> > > You say the denominator here is a u64, so do you not need to cast
> > > (u64)(5 * d1 * d2) to ensure it doesn't overflow the shift?
> > 
> > It should fit into u32. The maximum value should be
> > <= (5*0xf*0x7)<<22 based on the number of bits available
> 3b * 4b * 3b = 10b. So just fits.
> 
> Is it worth asserting those limits? Feels like it is running close, and
> will be subject to cargo-culting.

I suppose checking for it might be a good idea.

Just 'WARN_ON(5 * div1 * div2 >= 1 << 10)' maybe, or were you thinking
of something fancier?

-- 
Ville Syrjälä
Intel