[Intel-gfx] [PULL] gvt-next

Zhenyu Wang zhenyuw at linux.intel.com
Tue Apr 16 08:48:14 UTC 2019

On 2019.04.16 10:29:03 +0300, Joonas Lahtinen wrote:
> I'm getting an error while pulling this, could you check it:
>   From https://github.com/intel/gvt-linux
>    * tag                         gvt-next-2019-04-09 -> FETCH_HEAD
>   dim: 66bd9f69d615 ("drm/i915/gvt: addressed guest GPU hang with HWS index mode"): Fixes: SHA1 in not pointing at an ancestor:
>   dim:     54939ea0bd85 ("drm/i915: Switch to use HWS indices rather than addresses")
>   dim: ERROR: issues in commits detected, aborting

Sorry for this, I applied gvt change earlier than back-merge one, which caused this.
Now generated new one, pls help to pull.

The following changes since commit 28d618e9ab86f26a31af0b235ced55beb3e343c8:

  drm/i915: Update DRIVER_DATE to 20190404 (2019-04-04 17:43:58 +0300)

are available in the Git repository at:

  https://github.com/intel/gvt-linux.git tags/gvt-next-2019-04-16

for you to fetch changes up to 2bfc4975083ace0e5777116514c3a75e59b3dbcd:

  drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list (2019-04-16 16:52:51 +0800)


- Refine range of MCHBAR snapshot (Yakui)
- Refine out-of-sync page struct (Yakui)
- Remove unused vGPU sreg (Yan)
- Refind MMIO reg names (Xiaolin)
- Proper handling of sync/async flip (Colin)
- Proper handling of PIPE_CONTROL/MI_FLUSH_DW index mode (Xiaolin)
- EXCC reg mask fix (Colin)

Colin Xu (5):
      drm/i915/gvt: Use consist max display pipe numbers as i915 definition
      drm/i915/gvt: Add macro define for mmio 0x50080 and gvt flip event
      drm/i915/gvt: Enable synchronous flip on handling MI_DISPLAY_FLIP
      drm/i915/gvt: Enable async flip on plane surface mmio writes
      drm/i915/gvt: Fix incorrect mask of mmio 0x22028 in gen8/9 mmio list

Xiaolin Zhang (2):
      drm/i915/gvt: replaced register address with name
      drm/i915/gvt: addressed guest GPU hang with HWS index mode

Yan Zhao (1):
      drm/i915/gvt: remove the unused sreg

Zhao Yakui (2):
      drm/i915/gvt: Refine the snapshort range of I915 MCHBAR to optimize gvt-g boot time
      drm/i915/gvt: Refine the combined intel_vgpu_oos_page struct to save memory

Zhenyu Wang (1):
      Merge tag 'drm-intel-next-2019-04-04' into gvt-next

 drivers/gpu/drm/i915/gvt/cmd_parser.c   |  30 +++++-
 drivers/gpu/drm/i915/gvt/display.c      |   1 -
 drivers/gpu/drm/i915/gvt/gtt.c          |   7 ++
 drivers/gpu/drm/i915/gvt/gtt.h          |   2 +-
 drivers/gpu/drm/i915/gvt/gvt.h          |   9 +-
 drivers/gpu/drm/i915/gvt/handlers.c     | 159 +++++++++++++++++++-------------
 drivers/gpu/drm/i915/gvt/mmio.c         |   8 +-
 drivers/gpu/drm/i915/gvt/mmio_context.c |   4 +-
 drivers/gpu/drm/i915/gvt/reg.h          |  34 +++++++
 9 files changed, 172 insertions(+), 82 deletions(-)

Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 195 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20190416/09d731cf/attachment.sig>

More information about the Intel-gfx mailing list